mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time

After adjustment
Touch Pad CLK: 383.4 KHz
Touch Screen CLK: 381.6 KHz
Audio codec CLK: 386.0 KHz
TouchPad SDA hold time: 0.325ns

BUG=b:137722634
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage

Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Frank_Chu 2019-08-01 09:33:27 +08:00 committed by Martin Roth
parent b9df3bc5f7
commit 641e0f6841
1 changed files with 12 additions and 0 deletions

View File

@ -29,12 +29,24 @@ chip soc/intel/cannonlake
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 50,
.fall_time_ns = 15,
.data_hold_time_ns = 330,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 60,
.fall_time_ns = 25,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 150,
.fall_time_ns = 150,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 120,
.fall_time_ns = 120,
},
.gspi[0] = {
.speed_mhz = 1,