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sb/intel/lynxpoint: Use common code for early SMBus 

Looks like no one uses early SMBus for now, but that may change someday.

Change-Id: I42971662a279860a8c2e058fcb194fe5eba7c740
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42001
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-01 20:06:03 +02:00
parent d39e6b6d81
commit 64285775a0
3 changed files with 2 additions and 35 deletions
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1
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -9,6 +9,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE

2
src/southbridge/intel/lynxpoint/Makefile.inc
View File

@ -33,7 +33,7 @@ smm-y += smihandler.c me_9.x.c pch.c
smm-y += pmutil.c usb_ehci.c usb_xhci.c
bootblock-y += early_pch.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)

34
src/southbridge/intel/lynxpoint/early_smbus.c
View File

@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/smbus_host.h>
#include "pch.h"
uintptr_t smbus_base(void)
{
return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
{
/* Set the SMBus device statically. */
pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
return -1;
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */
pci_write_config8(dev, HOSTC, HST_EN);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
return 0;
}