GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

broadwell: Update PCIe configuration to follow BWG 

According to BIOS spec 8.14
B0:D28:F0[5:4] should be set to 11

BRANCH=none
BUG=chrome-os-partner:28234
TEST=build ok, boot to Auron and Samus
     make sure register is set and PCIE is working

Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360
Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217414
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9197
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kane Chen 2014-09-09 15:53:09 -07:00 committed by Patrick Georgi
parent 86b0c8b480
commit 642e598102
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/broadwell/pcie.c
View File

@ -113,6 +113,7 @@ static void root_port_init_config(device_t dev)
rpc.pin_ownership = pci_read_config32(dev, 0x410);
root_port_config_update_gbe_port();
pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
if (dev->chip_info != NULL) {
config_t *config = dev->chip_info;
rpc.coalesce = config->pcie_port_coalesce;