soc/amd: factor out common AOAC device enable and status query functions

The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.

Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/common/block/aoac/Kconfig

@@ -0,0 +1,6 @@
+config SOC_AMD_COMMON_BLOCK_AOAC
+	bool
+	default n
+	help
+	  Select this option to add the common functions for the AOAC block to
+	  the build.

src/soc/amd/common/block/aoac/Makefile.inc

@@ -0,0 +1,8 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_AOAC),y)
+
+bootblock-y += aoac.c
+romstage-y += aoac.c
+verstage-y += aoac.c
+ramstage-y += aoac.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_AOAC

src/soc/amd/common/block/aoac/aoac.c

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/aoac.h>
+
+/* This initiates the power on sequence, but doesn't wait for the device to be powered on. */
+void power_on_aoac_device(unsigned int dev)
+{
+	uint8_t byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
+	byte |= FCH_AOAC_PWR_ON_DEV;
+	byte &= ~FCH_AOAC_TARGET_DEVICE_STATE;
+	byte |= FCH_AOAC_D0_INITIALIZED;
+	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
+}
+
+void power_off_aoac_device(unsigned int dev)
+{
+	uint8_t byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
+	byte &= ~FCH_AOAC_PWR_ON_DEV;
+	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
+}
+
+bool is_aoac_device_enabled(unsigned int dev)
+{
+	uint8_t byte = aoac_read8(AOAC_DEV_D3_STATE(dev));
+	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
+	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
+		return true;
+	else
+		return false;
+}

src/soc/amd/common/block/include/amdblocks/aoac.h

@@ -32,4 +32,8 @@
 #define   FCH_AOAC_STAT0		BIT(6)
 #define   FCH_AOAC_STAT1		BIT(7)
 
+bool is_aoac_device_enabled(unsigned int dev);
+void power_on_aoac_device(unsigned int dev);
+void power_off_aoac_device(unsigned int dev);
+
 #endif /* AMD_BLOCK_AOAC_H */

src/soc/amd/picasso/Kconfig

@@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_ACPI
+	select SOC_AMD_COMMON_BLOCK_AOAC
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_PCI

src/soc/amd/picasso/aoac.c

@@ -30,40 +30,6 @@ const static unsigned int aoac_devs[] = {
 	FCH_AOAC_DEV_ESPI,
 };
 
-void power_on_aoac_device(unsigned int dev)
-{
-	uint8_t byte;
-
-	/* Power on the UART and AMBA devices */
-	byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
-	byte |= FCH_AOAC_PWR_ON_DEV;
-	byte &= ~FCH_AOAC_TARGET_DEVICE_STATE;
-	byte |= FCH_AOAC_D0_INITIALIZED;
-	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
-}
-
-void power_off_aoac_device(unsigned int dev)
-{
-	uint8_t byte;
-
-	/* Power off the UART and AMBA devices */
-	byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
-	byte &= ~FCH_AOAC_PWR_ON_DEV;
-	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
-}
-
-bool is_aoac_device_enabled(unsigned int dev)
-{
-	uint8_t byte;
-
-	byte = aoac_read8(AOAC_DEV_D3_STATE(dev));
-	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
-	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
-		return true;
-	else
-		return false;
-}
-
 void wait_for_aoac_enabled(unsigned int dev)
 {
 	while (!is_aoac_device_enabled(dev))

src/soc/amd/picasso/include/soc/southbridge.h

@@ -247,9 +247,6 @@ typedef struct aoac_devs {
 } __packed aoac_devs_t;
 
 void enable_aoac_devices(void);
-bool is_aoac_device_enabled(unsigned int dev);
-void power_on_aoac_device(unsigned int dev);
-void power_off_aoac_device(unsigned int dev);
 void wait_for_aoac_enabled(unsigned int dev);
 void sb_clk_output_48Mhz(void);
 void sb_enable(struct device *dev);

src/soc/amd/picasso/uart.c

@@ -6,6 +6,7 @@
 #include <device/mmio.h>
 #include <amdblocks/gpio_banks.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/aoac.h>
 #include <soc/southbridge.h>
 #include <soc/gpio.h>
 #include <soc/uart.h>

src/soc/amd/stoneyridge/Kconfig

@@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_ACPI
+	select SOC_AMD_COMMON_BLOCK_AOAC
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_PCI
 	select SOC_AMD_COMMON_BLOCK_HDA

src/soc/amd/stoneyridge/southbridge.c

@@ -146,28 +146,6 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
 	return irq_association;
 }
 
-static void power_on_aoac_device(unsigned int dev)
-{
-	uint8_t byte;
-
-	/* Power on the UART and AMBA devices */
-	byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
-	byte |= FCH_AOAC_PWR_ON_DEV;
-	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
-}
-
-static bool is_aoac_device_enabled(unsigned int dev)
-{
-	uint8_t byte;
-
-	byte = aoac_read8(AOAC_DEV_D3_STATE(dev));
-	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
-	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
-		return true;
-	else
-		return false;
-}
-
 void enable_aoac_devices(void)
 {
 	bool status;