soc/intel/xeon_sp/skx: Reorder soc_util.c
Reorder soc_util.c and remove the un-needed #if ENV_RAMSTAGE to match cpx version in preparation for more de-duplication. Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones
Marc Jones
parent
0a61ecef35
commit
645bca4810
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@ -45,18 +45,42 @@
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* +-------------------------+
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*/
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static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
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const struct SystemMemoryMapHob *get_system_memory_map(void)
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{
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size_t hob_size;
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const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
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const struct SystemMemoryMapHob *memmap_addr;
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memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
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assert(memmap_addr != NULL && hob_size != 0);
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return memmap_addr;
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}
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uint8_t get_iiostack_info(struct iiostack_resource *info)
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{
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size_t hob_size;
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const IIO_UDS *hob;
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const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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const IIO_UDS *hob;
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assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK);
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hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
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hob = fsp_find_extension_hob_by_guid(
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fsp_hob_iio_universal_data_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
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// copy IIO Stack info from FSP HOB
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info->no_of_stacks = 0;
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for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
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for (int x = 0; x < MAX_IIO_STACK; ++x) {
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const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
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// TODO: do we have situation with only bux 0 and one stack?
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if (ri->BusBase >= ri->BusLimit)
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continue;
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assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
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memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
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}
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}
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return hob->PlatformData.Pci64BitResourceAllocation;
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}
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/* return 1 if command timed out else 0 */
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@ -79,26 +103,6 @@ static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t ma
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return 0; /* successful */
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}
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/* return 1 if command timed out else 0 */
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static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
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uint32_t pcode_init_mask, uint32_t val)
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{
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uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
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pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
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uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
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reg &= (uint32_t) ~rst_cpl_mask;
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reg |= rst_cpl_mask;
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reg |= val;
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/* update BIOS RESET completion bit */
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pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
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/* wait for PCU ack */
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return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
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pcode_init_mask);
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}
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/* return 1 if command timed out else 0 */
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static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
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{
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@ -123,54 +127,38 @@ static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32
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BIOS_MB_RUN_BUSY_MASK, 0);
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}
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void config_reset_cpl3_csrs(void)
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static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
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{
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uint32_t data, plat_info, max_min_turbo_limit_ratio;
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size_t hob_size;
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const IIO_UDS *hob;
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const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
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assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK);
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hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
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}
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/* return 1 if command timed out else 0 */
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static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
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uint32_t pcode_init_mask, uint32_t val)
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{
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uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
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pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
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/* configure PCU_CR0_FUN csrs */
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pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
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data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
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data |= P_STATE_LIMITS_LOCK;
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pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
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uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
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reg &= (uint32_t) ~rst_cpl_mask;
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reg |= rst_cpl_mask;
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reg |= val;
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plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
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dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
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max_min_turbo_limit_ratio =
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(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
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MAX_NON_TURBO_LIM_RATIO_SHIFT;
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printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
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plat_info, max_min_turbo_limit_ratio);
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/* update BIOS RESET completion bit */
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pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
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/* configure PCU_CR1_FUN csrs */
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pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
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data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
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/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
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data &= 0x0fffffff;
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data |= SAPMCTL_LOCK_MASK;
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pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
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/* configure PCU_CR1_FUN csrs */
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pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
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data = PCIE_IN_PKGCSTATE_L1_MASK;
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pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
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data = KTI_IN_PKGCSTATE_L1_MASK;
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pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
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data = PROCHOT_RATIO;
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printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
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pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
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dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
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data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
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data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
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pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
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}
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/* wait for PCU ack */
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return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
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pcode_init_mask);
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}
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static void set_bios_init_completion_for_package(uint32_t socket)
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@ -229,43 +217,54 @@ void set_bios_init_completion(void)
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set_bios_init_completion_for_package(sbsp_socket_id);
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}
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uint8_t get_iiostack_info(struct iiostack_resource *info)
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void config_reset_cpl3_csrs(void)
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{
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size_t hob_size;
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const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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const IIO_UDS *hob;
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uint32_t data, plat_info, max_min_turbo_limit_ratio;
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hob = fsp_find_extension_hob_by_guid(
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fsp_hob_iio_universal_data_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
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uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
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// copy IIO Stack info from FSP HOB
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info->no_of_stacks = 0;
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for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
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for (int x = 0; x < MAX_IIO_STACK; ++x) {
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const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
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// TODO: do we have situation with only bux 0 and one stack?
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if (ri->BusBase >= ri->BusLimit)
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continue;
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assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
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memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
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/* configure PCU_CR0_FUN csrs */
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pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
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data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
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data |= P_STATE_LIMITS_LOCK;
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pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
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plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
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dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
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max_min_turbo_limit_ratio =
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(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
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MAX_NON_TURBO_LIM_RATIO_SHIFT;
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printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
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plat_info, max_min_turbo_limit_ratio);
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/* configure PCU_CR1_FUN csrs */
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pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
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data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
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/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
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data &= 0x0fffffff;
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data |= SAPMCTL_LOCK_MASK;
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pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
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/* configure PCU_CR1_FUN csrs */
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pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
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data = PCIE_IN_PKGCSTATE_L1_MASK;
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pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
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data = KTI_IN_PKGCSTATE_L1_MASK;
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pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
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data = PROCHOT_RATIO;
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printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
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pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
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dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
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data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
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data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
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pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
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}
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}
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return hob->PlatformData.Pci64BitResourceAllocation;
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}
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#if ENV_RAMSTAGE
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const struct SystemMemoryMapHob *get_system_memory_map(void)
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{
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size_t hob_size;
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const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
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const struct SystemMemoryMapHob *memmap_addr;
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memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
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assert(memmap_addr != NULL && hob_size != 0);
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return memmap_addr;
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}
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/*
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@ -296,4 +295,3 @@ int soc_get_stack_for_port(int port)
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else
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return -1;
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}
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#endif
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