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soc/intel/xeon_sp/skx: Reorder soc_util.c 

Reorder soc_util.c  and remove the un-needed #if ENV_RAMSTAGE to match
cpx version in preparation for more de-duplication.

Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones 2020-11-02 14:29:46 -07:00 committed by Marc Jones
parent 0a61ecef35
commit 645bca4810
1 changed files with 98 additions and 100 deletions
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198
src/soc/intel/xeon_sp/skx/soc_util.c
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@ -45,18 +45,42 @@
* +-------------------------+
*/
static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
const struct SystemMemoryMapHob *get_system_memory_map(void)
{
size_t hob_size;
const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
const struct SystemMemoryMapHob *memmap_addr;
memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
assert(memmap_addr != NULL && hob_size != 0);
return memmap_addr;
}
uint8_t get_iiostack_info(struct iiostack_resource *info)
{
size_t hob_size;
const IIO_UDS *hob;
const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
const IIO_UDS *hob;
assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK);
hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
hob = fsp_find_extension_hob_by_guid(
fsp_hob_iio_universal_data_guid, &hob_size);
assert(hob != NULL && hob_size != 0);
return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
// copy IIO Stack info from FSP HOB
info->no_of_stacks = 0;
for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
for (int x = 0; x < MAX_IIO_STACK; ++x) {
const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
// TODO: do we have situation with only bux 0 and one stack?
if (ri->BusBase >= ri->BusLimit)
continue;
assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
}
}
return hob->PlatformData.Pci64BitResourceAllocation;
}
/* return 1 if command timed out else 0 */
@ -79,26 +103,6 @@ static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t ma
return 0; /* successful */
}
/* return 1 if command timed out else 0 */
static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
uint32_t pcode_init_mask, uint32_t val)
{
uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
reg &= (uint32_t) ~rst_cpl_mask;
reg |= rst_cpl_mask;
reg |= val;
/* update BIOS RESET completion bit */
pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
/* wait for PCU ack */
return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
pcode_init_mask);
}
/* return 1 if command timed out else 0 */
static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
{
@ -123,54 +127,38 @@ static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32
BIOS_MB_RUN_BUSY_MASK, 0);
}
void config_reset_cpl3_csrs(void)
static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
{
uint32_t data, plat_info, max_min_turbo_limit_ratio;
size_t hob_size;
const IIO_UDS *hob;
const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK);
/* configure PCU_CR0_FUN csrs */
pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
data |= P_STATE_LIMITS_LOCK;
pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
assert(hob != NULL && hob_size != 0);
plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
max_min_turbo_limit_ratio =
(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
MAX_NON_TURBO_LIM_RATIO_SHIFT;
printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
plat_info, max_min_turbo_limit_ratio);
return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
}
/* configure PCU_CR1_FUN csrs */
pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
/* return 1 if command timed out else 0 */
static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
uint32_t pcode_init_mask, uint32_t val)
{
uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
data &= 0x0fffffff;
data |= SAPMCTL_LOCK_MASK;
pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
reg &= (uint32_t) ~rst_cpl_mask;
reg |= rst_cpl_mask;
reg |= val;
/* configure PCU_CR1_FUN csrs */
pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
/* update BIOS RESET completion bit */
pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
data = PCIE_IN_PKGCSTATE_L1_MASK;
pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
data = KTI_IN_PKGCSTATE_L1_MASK;
pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
data = PROCHOT_RATIO;
printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
}
/* wait for PCU ack */
return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
pcode_init_mask);
}
static void set_bios_init_completion_for_package(uint32_t socket)
@ -229,43 +217,54 @@ void set_bios_init_completion(void)
set_bios_init_completion_for_package(sbsp_socket_id);
}
uint8_t get_iiostack_info(struct iiostack_resource *info)
void config_reset_cpl3_csrs(void)
{
size_t hob_size;
const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
const IIO_UDS *hob;
uint32_t data, plat_info, max_min_turbo_limit_ratio;
hob = fsp_find_extension_hob_by_guid(
fsp_hob_iio_universal_data_guid, &hob_size);
assert(hob != NULL && hob_size != 0);
for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
// copy IIO Stack info from FSP HOB
info->no_of_stacks = 0;
for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
for (int x = 0; x < MAX_IIO_STACK; ++x) {
const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
// TODO: do we have situation with only bux 0 and one stack?
if (ri->BusBase >= ri->BusLimit)
continue;
assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
}
/* configure PCU_CR0_FUN csrs */
pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
data |= P_STATE_LIMITS_LOCK;
pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
max_min_turbo_limit_ratio =
(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
MAX_NON_TURBO_LIM_RATIO_SHIFT;
printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
plat_info, max_min_turbo_limit_ratio);
/* configure PCU_CR1_FUN csrs */
pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
data &= 0x0fffffff;
data |= SAPMCTL_LOCK_MASK;
pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
/* configure PCU_CR1_FUN csrs */
pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
data = PCIE_IN_PKGCSTATE_L1_MASK;
pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
data = KTI_IN_PKGCSTATE_L1_MASK;
pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
data = PROCHOT_RATIO;
printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
}
return hob->PlatformData.Pci64BitResourceAllocation;
}
#if ENV_RAMSTAGE
const struct SystemMemoryMapHob *get_system_memory_map(void)
{
size_t hob_size;
const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
const struct SystemMemoryMapHob *memmap_addr;
memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
assert(memmap_addr != NULL && hob_size != 0);
return memmap_addr;
}
/*
@ -296,4 +295,3 @@ int soc_get_stack_for_port(int port)
else
return -1;
}
#endif