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soc/intel/skylake: don't hardcode GPE0 standard reg 

While using '3' is fine for the standard gpe0 for skylake, I want
to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX
without the hard coded index. If that does happen now things will
still work, but it may just not match the hardware proper.

BUG=chrome-os-partner:58666

Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17160
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2016-10-27 09:53:17 -05:00
parent 11afdbf67c
commit 64606cea93
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/skylake/acpi.c
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@ -598,6 +598,7 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
uint32_t pm1_en; uint32_t pm1_en;
uint32_t gpe0_std; uint32_t gpe0_std;
int i; int i;
const int last_index = GPE0_REG_MAX - 1;
ps = cbmem_find(CBMEM_ID_POWER_STATE); ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps == NULL) if (ps == NULL)
@ -622,9 +623,9 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
/* Mask off GPE0 status bits that are not enabled */ /* Mask off GPE0 status bits that are not enabled */
*gpe0 = &gpe0_sts[0]; *gpe0 = &gpe0_sts[0];
for (i = 0; i < (GPE0_REG_MAX-1); i++) for (i = 0; i < last_index; i++)
gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
gpe0_sts[3] = ps->gpe0_sts[3] & gpe0_std; gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std;
return GPE0_REG_MAX; return GPE0_REG_MAX;
} }