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mb/google/hatch/var/dratini: Update DPTF parameters 

1. Add a TEMP_SENSOR3
2. Update DFPS (fan performance state) table with values received
   from thermal team
3. Update PL1 override to 15W
4. Update PL2 override to 51W

BRANCH=hatch
BUG=b:147792204
TEST=build and verify by thermal team

Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wisley Chen 2019-12-31 13:26:04 +08:00 committed by Patrick Georgi
parent a211298d20
commit 6476e41512
2 changed files with 26 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl
View File

@ -38,6 +38,11 @@
#define DPTF_TSR1_ACTIVE_AC5 36 #define DPTF_TSR1_ACTIVE_AC5 36
#define DPTF_TSR1_ACTIVE_AC6 33 #define DPTF_TSR1_ACTIVE_AC6 33
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU"
#define DPTF_TSR2_PASSIVE 105
#define DPTF_TSR2_CRITICAL 105
#define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_CHARGER
#define DPTF_ENABLE_FAN_CONTROL #define DPTF_ENABLE_FAN_CONTROL
@ -57,15 +62,15 @@ Name (DFPS, Package () {
* These are initial reference values. * These are initial reference values.
*/ */
/* Control, Trip Point, Speed, NoiseLevel, Power */ /* Control, Trip Point, Speed, NoiseLevel, Power */
Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, Package () {100, 0xFFFFFFFF, 6700, 220, 2200},
Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, Package () {90, 0xFFFFFFFF, 5800, 180, 1800},
Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, Package () {80, 0xFFFFFFFF, 5000, 145, 1450},
Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, Package () {70, 0xFFFFFFFF, 4900, 115, 1150},
Package () {50, 0xFFFFFFFF, 3838, 90, 900}, Package () {63, 0xFFFFFFFF, 3838, 90, 900},
Package () {40, 0xFFFFFFFF, 2904, 55, 550}, Package () {58, 0xFFFFFFFF, 2904, 55, 550},
Package () {30, 0xFFFFFFFF, 2337, 30, 300}, Package () {54, 0xFFFFFFFF, 2337, 30, 300},
Package () {20, 0xFFFFFFFF, 1608, 15, 150}, Package () {50, 0xFFFFFFFF, 1608, 15, 150},
Package () {10, 0xFFFFFFFF, 800, 10, 100}, Package () {45, 0xFFFFFFFF, 800, 10, 100},
Package () {0, 0xFFFFFFFF, 0, 0, 50} Package () {0, 0xFFFFFFFF, 0, 0, 50}
}) })
@ -84,6 +89,11 @@ Name (DART, Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 70, 60, 50, 40, 30, \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 70, 60, 50, 40, 30,
0, 0, 0 0, 0, 0
}, },
Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 100, 80, 70, 60, 50, 40, 30,
0, 0, 0
},
}) })
Name (DTRT, Package () { Name (DTRT, Package () {
@ -96,6 +106,9 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU (TSR1) */ /* CPU Throttle Effect on CPU (TSR1) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
/* CPU Throttle Effect on CPU (TSR2) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()
@ -112,8 +125,8 @@ Name (MPPC, Package ()
Package () { /* Power Limit 2 */ Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
15000, /* PowerLimitMinimum */ 15000, /* PowerLimitMinimum */
25000, /* PowerLimitMaximum */ 51000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */ 51000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */ 32000, /* TimeWindowMaximum */
1000 /* StepSize */ 1000 /* StepSize */
} }

2
src/mainboard/google/hatch/variants/dratini/overridetree.cb
View File

@ -1,4 +1,6 @@
chip soc/intel/cannonlake chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,