mb/google/hatch/var/dratini: Update DPTF parameters
1. Add a TEMP_SENSOR3 2. Update DFPS (fan performance state) table with values received from thermal team 3. Update PL1 override to 15W 4. Update PL2 override to 51W BRANCH=hatch BUG=b:147792204 TEST=build and verify by thermal team Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -38,6 +38,11 @@
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#define DPTF_TSR1_ACTIVE_AC5 36
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#define DPTF_TSR1_ACTIVE_AC6 33
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU"
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#define DPTF_TSR2_PASSIVE 105
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#define DPTF_TSR2_CRITICAL 105
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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@ -57,15 +62,15 @@ Name (DFPS, Package () {
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* These are initial reference values.
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*/
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {50, 0xFFFFFFFF, 3838, 90, 900},
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Package () {40, 0xFFFFFFFF, 2904, 55, 550},
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Package () {30, 0xFFFFFFFF, 2337, 30, 300},
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Package () {20, 0xFFFFFFFF, 1608, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {100, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {90, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {80, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {70, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {63, 0xFFFFFFFF, 3838, 90, 900},
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Package () {58, 0xFFFFFFFF, 2904, 55, 550},
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Package () {54, 0xFFFFFFFF, 2337, 30, 300},
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Package () {50, 0xFFFFFFFF, 1608, 15, 150},
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Package () {45, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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})
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@ -84,6 +89,11 @@ Name (DART, Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 70, 60, 50, 40, 30,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 100, 80, 70, 60, 50, 40, 30,
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0, 0, 0
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},
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})
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Name (DTRT, Package () {
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@ -96,6 +106,9 @@ Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU (TSR1) */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
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/* CPU Throttle Effect on CPU (TSR2) */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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@ -112,8 +125,8 @@ Name (MPPC, Package ()
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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15000, /* PowerLimitMinimum */
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25000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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51000, /* PowerLimitMaximum */
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51000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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@ -1,4 +1,6 @@
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chip soc/intel/cannonlake
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register "tdp_pl1_override" = "15"
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register "tdp_pl2_override" = "51"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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