From 6478cf9702946016c235d1267fba76254cb906a1 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 30 Mar 2021 23:20:08 +0200
Subject: [PATCH] mb/google/guybrush: add DXIO and DDI descriptors

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 .../google/guybrush/port_descriptors.c        | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index d407fe9302..b0f4fa9ba9 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -3,10 +3,81 @@
 #include <soc/platform_descriptors.h>
 #include <types.h>
 
+/* TODO: test if this really works */
 static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
+	{ /* WLAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
+		.device_number = 2,
+		.function_number = 1,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* SD */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 1,
+		.end_logical_lane = 1,
+		.device_number = 2,
+		.function_number = 2,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* WWAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 2,
+		.end_logical_lane = 2,
+		.device_number = 2,
+		.function_number = 3,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ2,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* NVME */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 4,
+		.end_logical_lane = 7,
+		.device_number = 2,
+		.function_number = 4,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ3,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	}
 };
 
+/* TODO: verify the DDI table, since this is mostly an educated guess right now */
 static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = {
+	{ /* DDI0 - eDP */
+		.connector_type = DDI_EDP,
+		.aux_index = DDI_AUX1,
+		.hdp_index = DDI_HDP1
+	},
+	{ /* DDI1 - HDMI */
+		.connector_type = DDI_HDMI,
+		.aux_index = DDI_AUX2,
+		.hdp_index = DDI_HDP2
+	},
+	{ /* DDI2 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI3 - DP (type C) */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI4 - DP (type C) */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX4,
+		.hdp_index = DDI_HDP4,
+	}
 };
 
 void mainboard_get_dxio_ddi_descriptors(