From 647a7bb7776c64e63dc3c7d553e733cbdc9f5e1f Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Thu, 15 Jul 2021 14:17:39 +0530
Subject: [PATCH] soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS

This patch removes leading zero from CPUIDs as below:
0x05065a -> 0x5065a
0x05065b -> 0x5065b

Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
---
 src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
index 693de8fbcc..716fe29ead 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
@@ -6,8 +6,8 @@
 #include <device/device.h>
 #include <cpu/x86/msr.h>
 
-#define CPUID_COOPERLAKE_SP_A0			0x05065a
-#define CPUID_COOPERLAKE_SP_A1			0x05065b
+#define CPUID_COOPERLAKE_SP_A0			0x5065a
+#define CPUID_COOPERLAKE_SP_A1			0x5065b
 
 void cpx_init_cpus(struct device *dev);