sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7
Tested on Intel D510MO Before this patch, I was unable to get the SATA controller into AHCI mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus. With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1 Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7) No regressions detected. Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12923 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Damien Zammit
Martin Roth
parent
fb87998150
commit
647e385187
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@ -18,6 +18,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include "i82801gx.h"
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#include "sata.h"
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#if !CONFIG_MMCONF_SUPPORT_DEFAULT
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#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT
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@ -31,6 +32,11 @@ void i82801gx_enable(device_t dev)
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_SERR;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
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printk(BIOS_DEBUG, "Set SATA mode early\n");
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sata_enable(dev);
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}
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}
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struct chip_operations southbridge_intel_i82801gx_ops = {
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -19,14 +20,56 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82801gx.h"
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#include "sata.h"
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typedef struct southbridge_intel_i82801gx_config config_t;
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static u8 get_ich7_sata_ports(void)
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{
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struct device *lpc;
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lpc = dev_find_slot(0, PCI_DEVFN(31, 0));
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switch (pci_read_config16(lpc, PCI_DEVICE_ID)) {
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case 0x27b0:
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case 0x27b8:
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return 0xf;
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case 0x27b9:
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case 0x27bd:
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return 0x5;
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case 0x27bc:
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return 0x3;
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default:
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printk(BIOS_ERR,
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"i82801gx_sata: error: cannot determine port config\n");
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return 0;
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}
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}
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void sata_enable(struct device *dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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if (config->sata_ahci) {
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/* Set map to ahci */
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pci_write_config8(dev, SATA_MAP,
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(pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40);
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} else {
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/* Set map to ide */
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pci_write_config8(dev, SATA_MAP,
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pci_read_config8(dev, SATA_MAP) & ~0xc3);
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}
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/* At this point, the new pci id will appear on the bus */
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}
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static void sata_init(struct device *dev)
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{
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u32 reg32;
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u16 reg16;
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u32 *ahci_bar;
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u8 ports;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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@ -38,7 +81,8 @@ static void sata_init(struct device *dev)
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return;
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}
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/* SATA configuration */
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/* Get ICH7 SATA port config */
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ports = get_ich7_sata_ports();
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND, 0x0007);
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@ -70,13 +114,10 @@ static void sata_init(struct device *dev)
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Combine IDE - SATA configuration */
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pci_write_config8(dev, 0x90, 0x02);
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pci_write_config8(dev, SATA_MAP, 0x02);
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/* Port 0 & 1 enable */
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pci_write_config8(dev, 0x92, 0x0f);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94, 0x5a000180);
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pci_write_config8(dev, SATA_PCS, 0x0f);
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} else if(config->sata_ahci) {
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printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
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/* Allow both Legacy and Native mode */
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@ -86,38 +127,18 @@ static void sata_init(struct device *dev)
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0x0a);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Set Sata Controller Mode. */
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pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
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/* In ACHI mode, bit[3:0] must always be set
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* (Port status is controlled through AHCI BAR)
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* Different settings for different controller models.
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*/
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pci_write_config8(dev, 0x92, 0x0f);
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pci_write_config8(dev, SATA_PCS, ports);
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ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
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ahci_bar[3] = config->sata_ports_implemented;
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94, 0x1a000180);
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} else {
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printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
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/* Set Sata Controller Mode. No Mapping(?) */
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pci_write_config8(dev, 0x90, 0x00);
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pci_write_config8(dev, SATA_MAP, 0x00);
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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@ -153,12 +174,12 @@ static void sata_init(struct device *dev)
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Port 0 & 1 enable XXX */
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pci_write_config8(dev, 0x92, 0x15);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94, 0x1a000180);
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pci_write_config8(dev, SATA_PCS, 0x15);
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}
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/* Enable clock gating for unused ports and set initialization reg */
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pci_write_config32(dev, SATA_IR, SIF3(ports) | SIF2 | SIF1 | SCRE);
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/* All configurations need this SATA initialization sequence */
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pci_write_config8(dev, 0xa0, 0x40);
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pci_write_config8(dev, 0xa6, 0x22);
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@ -179,9 +200,9 @@ static void sata_init(struct device *dev)
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pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
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/* Sata Initialization Register */
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reg32 = pci_read_config32(dev, 0x94);
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reg32 |= (1 << 30); // due to some bug
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pci_write_config32(dev, 0x94, reg32);
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reg32 = pci_read_config32(dev, SATA_IR);
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reg32 |= SCRD; // due to some bug
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pci_write_config32(dev, SATA_IR, reg32);
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}
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static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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@ -211,11 +232,11 @@ static struct device_operations sata_ops = {
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static const unsigned short sata_ids[] = {
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0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
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/* NOTE: Any of the below are not properly supported yet. */
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0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
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0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
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/* NOTE: Any of the below are not properly supported yet. */
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0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */
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0
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};
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@ -0,0 +1,31 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef I82801GX_SATA_H
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#define I82801GX_SATA_H
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#define SATA_MAP 0x90
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#define SATA_PCS 0x92
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#define SATA_IR 0x94
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#define SIF1 0x180
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#define SIF2 (1 << 23)
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#define SIF3(ports) ((~(ports) & 0xf) << 24)
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#define SCRE (1 << 28)
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#define SCRD (1 << 30)
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void sata_enable(struct device *dev);
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#endif
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