gm45: Ensure that brightness register in gma contains sane value.
Change-Id: Ia66c71c3adf2ae0d413750b5e59e3eaba3888a0b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6587 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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@ -35,5 +35,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
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ramstage-y += ram_calc.c
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ramstage-y += northbridge.c
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ramstage-y += gma.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += delay.c
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@ -0,0 +1,99 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Chromium OS Authors
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* Copyright (C) 2013 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <string.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include "drivers/intel/gma/i915_reg.h"
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#include "chip.h"
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#include "gm45.h"
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static struct resource *gtt_res = NULL;
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static inline void gtt_write(u32 reg, u32 data)
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{
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write32(gtt_res->base + reg, data);
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}
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static void gma_func0_init(struct device *dev)
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{
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u32 reg32;
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/* IGD needs to be Bus Master */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Init graphics power management */
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gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
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/* PCI Init, will run VBIOS */
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pci_dev_init(dev);
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/* Post VBIOS init */
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/* Enable Backlight */
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gtt_write(BLC_PWM_CTL2, (1 << 31));
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gtt_write(BLC_PWM_CTL, 0x06100610);
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}
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static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor &
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0xffff));
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}
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}
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static struct pci_operations gma_pci_ops = {
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.set_subsystem = gma_set_subsystem,
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};
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static struct device_operations gma_func0_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = gma_func0_init,
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.scan_bus = 0,
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.enable = 0,
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.ops_pci = &gma_pci_ops,
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};
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static const unsigned short pci_device_ids[] =
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{
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0x2a42, 0
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};
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static const struct pci_driver gma __pci_driver = {
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.ops = &gma_func0_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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