gm45: Ensure that brightness register in gma contains sane value.

Change-Id: Ia66c71c3adf2ae0d413750b5e59e3eaba3888a0b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6587
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-08-10 23:48:11 +02:00
parent 8845759a02
commit 6481e1052f
2 changed files with 100 additions and 0 deletions

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@ -35,5 +35,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += delay.c

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@ -0,0 +1,99 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Chromium OS Authors
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include "drivers/intel/gma/i915_reg.h"
#include "chip.h"
#include "gm45.h"
static struct resource *gtt_res = NULL;
static inline void gtt_write(u32 reg, u32 data)
{
write32(gtt_res->base + reg, data);
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
/* Post VBIOS init */
/* Enable Backlight */
gtt_write(BLC_PWM_CTL2, (1 << 31));
gtt_write(BLC_PWM_CTL, 0x06100610);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor &
0xffff));
}
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
};
static const unsigned short pci_device_ids[] =
{
0x2a42, 0
};
static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};