small gcc4 patches, some ts5300 updates

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/include/pc80/ide.h

@@ -207,7 +207,5 @@ struct ide_pio_command
 /* Maximum block_size that may be set. */
 #define DISK_BUFFER_SIZE (18 * SECTOR_SIZE)
 
-extern struct harddisk_info harddisk_info[];
-
 extern int ide_probe(int drive);
 extern int ide_read(int drive, sector_t sector, void *buffer);

src/mainboard/technologic/ts5300/Config.lb

@@ -5,7 +5,7 @@
 default ROM_SIZE = 512 * 1024 
 default FALLBACK_SIZE = 0x10000
 if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = 64 * 1024 # FALLBACK_SIZE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
 	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
 else
 	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
@@ -108,6 +108,11 @@ if USE_FALLBACK_IMAGE
 	mainboardinit ./failover.inc
 end
 
+
+# VGA console
+if CONFIG_CONSOLE_VGA
+	default CONFIG_PCI_ROM_RUN=1
+end
 ###
 ### O.k. We aren't just an intermediary anymore!
 ###
@@ -122,13 +127,22 @@ mainboardinit ./auto.inc
 ## Include the secondary Configuration files 
 ##
 dir /pc80
+dir /devices
 config chip.h
 
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-		device pci 1.0 on end
+	
+		chip drivers/pci/onboard
+			device pci 12.0 on end # enet
+		end
+		chip drivers/pci/onboard
+			device pci 14.0 on end # 69000
+			register "rom_address" = "0x2000000"
+		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end
+
 end

src/mainboard/technologic/ts5300/Options.lb

@@ -5,7 +5,9 @@ uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
 uses HAVE_OPTION_TABLE
 uses USE_OPTION_TABLE
+uses CONFIG_COMPRESS
 uses CONFIG_ROM_STREAM
+uses CONFIG_USE_INIT
 uses IRQ_SLOT_COUNT
 uses MAINBOARD
 uses MAINBOARD_VENDOR
@@ -27,15 +29,27 @@ uses _RAMBASE
 uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 uses HAVE_MP_TABLE
-uses HAVE_ACPI_TABLES
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
 uses OBJCOPY
+
+uses CONFIG_CONSOLE_SERIAL8250
+
+
 uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_COMPRESS
 
+# VGA support
+uses CONFIG_CONSOLE_VGA
+#uses CONFIG_LEGACY_VGABIOS
+#uses VGABIOS_START
+uses CONFIG_PCI_ROM_RUN
+
+
+default CONFIG_CONSOLE_SERIAL8250=1
+default DEFAULT_CONSOLE_LOGLEVEL=9
+default MAXIMUM_CONSOLE_LOGLEVEL=9
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
 
@@ -62,7 +76,8 @@ default HAVE_HARD_RESET=1
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
+default IRQ_SLOT_COUNT=7
+#object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
@@ -100,9 +115,9 @@ default CONFIG_ROM_STREAM     = 1
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
 default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 end
 
+

src/mainboard/technologic/ts5300/mainboard.c

@@ -3,9 +3,146 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <cpu/amd/sc520.h>
 #include "chip.h"
 
+
+static void irqdump()
+{
+  volatile unsigned char *irq;
+  void *mmcr;
+
+
+  int i;
+  int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
+	        0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
+		0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 
+		0xd30, 0xd31, 0xd32, 0xd33,
+		0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, 
+		0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, 
+		-1};
+  mmcr = (void *) 0xfffef000;
+
+  printk_err("mmcr is %p\n", mmcr);
+  for(i = 0; irqlist[i] >= 0; i++) {
+    irq = mmcr + irqlist[i];
+    printk_err("0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
+  }
+
+}
+
+/* TODO: finish up mmcr struct in sc520.h, and;
+   - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
+*/
+static void enable_dev(struct device *dev) {
+	extern unsigned char *rom_start, *rom_end;
+	volatile struct mmcrpic *pic = MMCRPIC;
+	volatile struct mmcr *mmcr = MMCRDEFAULT;
+
+	/* ts5300 has this register set to a weird value. 
+	 * follow the board, not the manual!
+	 */
+
+	/* currently, nothing in the device to use, so ignore it. */
+	printk_err("Technologic Systems 5300 ENTER %s\n", __FUNCTION__);
+
+
+	/* from fuctory bios */
+	/* NOTE: the following interrupt settings made interrupts work
+	 * for hard drive, and serial, but not for ethernet 
+	 */
+	/* just do what they say and nobody gets hurt. */
+	mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
+	/* all ints to level */
+	mmcr->pic.mpicmode = 0;
+	mmcr->pic.sl1picmode = 0;
+	mmcr->pic.sl2picmode = 0x80;
+
+	mmcr->pic.intpinpol = 0;
+
+	mmcr->pic.pit0map = 1;
+	mmcr->pic.uart1map = 0xc;
+	mmcr->pic.uart2map = 0xb;
+	mmcr->pic.rtcmap = 3;
+	mmcr->pic.ferrmap = 8;
+	mmcr->pic.gp0imap = 6;
+	mmcr->pic.gp1imap = 2;
+	mmcr->pic.gp2imap = 7;
+	mmcr->pic.gp6imap = 0x15;
+	mmcr->pic.gp7imap = 0x16;
+	mmcr->pic.gp10imap = 0x9;
+	mmcr->pic.gp9imap = 0x4;
+
+
+
+
+
+	irqdump();
+	printk_err("uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
+
+	printk_err("0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
+	printk_err("0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
+
+	/* The following block has NOT proven sufficient to get
+	 * the VGA hardware to talk to us 
+	 */
+	/* let's set some mmcr stuff per the BIOS settings */
+	mmcr->dbctl.dbctl = 0x10;
+	mmcr->sysarb.ctl = 6;
+	mmcr->sysarb.menb = 0xf;
+	mmcr->sysarb.prictl = 0xc0000f0f;
+	/* this is bios setting, depends on sysarb above */
+	mmcr->hostbridge.ctl = 0x108;
+	printk_err("TS5300 EXIT %s\n", __FUNCTION__);
+
+	/* pio */
+	mmcr->pio.data31_16 = 0xffbf;
+
+	/* pci stuff */
+	mmcr->pic.pciintamap = 0xa;
+
+	/* END block where vga hardware still will not talk to us */
+	/* all we get from VGA I/O addresses are ffff etc.
+	 */
+	mmcr->sysmap.adddecctl = 0x10;
+
+	/* VGA now talks to us, so this adddecctl was the trick. 
+	 * still no interrupts from enet. 
+	 * Let's try fixing the piodata stuff, as there may be 
+	 * some wire there not documented.
+	 */
+	mmcr->pio.data31_16 = 0xffbf;
+	/* also, our sl?picmode needs to match fuctory bios */
+	mmcr->pic.sl1picmode = 0x80;
+	mmcr->pic.sl2picmode = 0x0;
+	/* and, finally, they do set gp5imap and we don't. 
+	 */
+	mmcr->pic.gp5imap = 0xd;
+	/* remaining problem: almost certainly, the irq table is bogus
+	 * NO SHOCK as it came from fuctory bios. 
+	 * but let's try these 4 changes for now and see what shakes.
+	 */
+	/* still not interrupts. */
+	/* their IRQ table is wrong. Just hardwire it */
+	{
+	  char pciints[4] = {15, 15, 15, 15};
+	  pci_assign_irqs(0, 12, pciints);
+	}
+	/* the assigned failed but we just noticed -- there is no
+	 * dma mapping, and selftest on e100 requires that dma work
+	 */
+	/* follow fuctory here */
+	mmcr->dmacontrol.extchanmapa = 0x3210;
+
+	/* hack for IDIOTIC need to fix rom_start */
+	printk_err("Patching rom_start due to sc520 limits\n");
+	rom_start = 0x2000000 + 0x40000;
+	rom_end = rom_start + PAYLOAD_SIZE - 1;
+
+	
+}
 struct chip_operations mainboard_technologic_ts5300_ops = {
 	CHIP_NAME("Technologic Systems TS5300 mainboard ")
+	.enable_dev = enable_dev
 };
 

src/mainboard/technologic/ts5300/reset.c

@@ -32,12 +32,10 @@ static unsigned pci_read_config32(device_t dev, unsigned where)
         outl(0x80000000 | (addr & ~3), 0xCF8);
         return inl(0xCFC);
 }
-
+#endif
-#include "../../../northbridge/amd/amdk8/reset_test.c"
-
 void hard_reset(void)
 {
-	set_bios_reset();
+	//set_bios_reset();
-	pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+	//pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
 }
-#endif
+