From 648ed149a14c217bc84b0e4414fb49c8a626c7cb Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Fri, 27 Oct 2023 12:38:22 +0800 Subject: [PATCH] mb/google/rex: add dptf settings for 2+4 SOC SKU This patches privides settings based on 2+8 15w. BUG=b:306543967 TEST=boot on rex with 2+4 SOC and power limit settings are overridden correctly in variant_update_cpu_power_limits Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00 Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688 Reviewed-by: Sumeet R Pawnikar Reviewed-by: Subrata Banik Reviewed-by: Jamie Ryu Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- .../rex/variants/baseboard/rex/ramstage.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index f33db733fa..d2adaaee52 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -20,6 +20,15 @@ const struct cpu_tdp_power_limits performance_efficient_limits[] = { .pl2_max_power = 57000, .pl4_power = 114000 }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 57000, + .pl2_max_power = 57000, + .pl4_power = 114000 + }, }; const struct cpu_tdp_power_limits power_optimized_limits[] = { @@ -32,6 +41,15 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = { .pl2_max_power = 57000, .pl4_power = 64000 }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 57000, + .pl2_max_power = 57000, + .pl4_power = 64000 + }, }; void variant_devtree_update(void)