soc/mainboard: Update mainboard UART Kconfig
After f5ca922
(Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
parent
dd217362d4
commit
64925b5128
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@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_DRAGONEGG
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_ICELAKE
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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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@ -75,4 +76,7 @@ config INCLUDE_NHLT_BLOBS
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select NHLT_RT5663
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select NHLT_MAX98927
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_USES_FSP2_0
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select NO_FADT_8042
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@ -97,4 +98,7 @@ config INCLUDE_NHLT_BLOBS_KARMA
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select NHLT_DMIC_4CH
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select NHLT_MAX98357
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config UART_FOR_CONSOLE
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int
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default 2
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endif # BOARD_GOOGLE_BASEBOARD_FIZZ
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@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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@ -96,4 +97,8 @@ config GBB_HWID
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default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
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default "LARS TEST 5001" if BOARD_GOOGLE_LARS
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default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_TPM2
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@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select SOC_ESPI
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select MAINBOARD_HAS_SPI_TPM_CR50
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@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_USES_FSP2_0
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select SOC_INTEL_KABYLAKE
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@ -214,4 +215,7 @@ config VBOOT
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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select VBOOT_LID_SWITCH
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config UART_FOR_CONSOLE
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int
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default 2
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endif # BOARD_GOOGLE_BASEBOARD_POPPY
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@ -12,6 +12,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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@ -11,6 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
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select GENERIC_SPD_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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@ -82,6 +83,10 @@ config MAX_CPUS
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int
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default 8
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config UART_FOR_CONSOLE
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int
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default 2
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config VARIANT_DIR
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string
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default "arcada" if BOARD_GOOGLE_ARCADA
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_INTEL_APOLLOLAKE
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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config MAINBOARD_DIR
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string
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@ -18,4 +19,6 @@ config MAINBOARD_VENDOR
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string
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default "Intel"
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config UART_FOR_CONSOLE
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default 2
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endif
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@ -7,6 +7,7 @@ config BOARD_INTEL_BASEBOARD_GLKRVP
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select DRIVERS_I2C_HID
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select DRIVERS_GENERIC_MAX98357A
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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select SOC_INTEL_SKYLAKE
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@ -72,4 +73,8 @@ config GBB_HWID
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string
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depends on CHROMEOS
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default "KUNIMITSU TEST 8819"
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SERIRQ_CONTINUOUS_MODE
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select SKYLAKE_SOC_PCH_H
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select SOC_INTEL_SKYLAKE
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@ -4,6 +4,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SOC_INTEL_SKYLAKE
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# Workaround for EC/KBC IRQ1
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select SERIRQ_CONTINUOUS_MODE
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