soc/mainboard: Update mainboard UART Kconfig

After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Lijian Zhao 2019-01-11 07:54:48 -08:00 committed by Nico Huber
parent dd217362d4
commit 64925b5128
14 changed files with 37 additions and 0 deletions

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@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_DRAGONEGG
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_ICELAKE

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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
@ -75,4 +76,7 @@ config INCLUDE_NHLT_BLOBS
select NHLT_RT5663
select NHLT_MAX98927
config UART_FOR_CONSOLE
int
default 2
endif

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@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
@ -97,4 +98,7 @@ config INCLUDE_NHLT_BLOBS_KARMA
select NHLT_DMIC_4CH
select NHLT_MAX98357
config UART_FOR_CONSOLE
int
default 2
endif # BOARD_GOOGLE_BASEBOARD_FIZZ

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@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
@ -96,4 +97,8 @@ config GBB_HWID
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
default "LARS TEST 5001" if BOARD_GOOGLE_LARS
default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY
config UART_FOR_CONSOLE
int
default 2
endif

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@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2

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@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select SOC_ESPI
select MAINBOARD_HAS_SPI_TPM_CR50

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@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_KABYLAKE
@ -214,4 +215,7 @@ config VBOOT
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select VBOOT_LID_SWITCH
config UART_FOR_CONSOLE
int
default 2
endif # BOARD_GOOGLE_BASEBOARD_POPPY

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@ -12,6 +12,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2

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@ -11,6 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
@ -82,6 +83,10 @@ config MAX_CPUS
int
default 8
config UART_FOR_CONSOLE
int
default 2
config VARIANT_DIR
string
default "arcada" if BOARD_GOOGLE_ARCADA

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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_APOLLOLAKE
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
config MAINBOARD_DIR
string
@ -18,4 +19,6 @@ config MAINBOARD_VENDOR
string
default "Intel"
config UART_FOR_CONSOLE
default 2
endif

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@ -7,6 +7,7 @@ config BOARD_INTEL_BASEBOARD_GLKRVP
select DRIVERS_I2C_HID
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select DRIVERS_GENERIC_MAX98357A

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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select SOC_INTEL_SKYLAKE
@ -72,4 +73,8 @@ config GBB_HWID
string
depends on CHROMEOS
default "KUNIMITSU TEST 8819"
config UART_FOR_CONSOLE
int
default 2
endif

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@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select INTEL_LPSS_UART_FOR_CONSOLE
select SERIRQ_CONTINUOUS_MODE
select SKYLAKE_SOC_PCH_H
select SOC_INTEL_SKYLAKE

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@ -4,6 +4,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select SOC_INTEL_SKYLAKE
# Workaround for EC/KBC IRQ1
select SERIRQ_CONTINUOUS_MODE