soc/amd/common/cpu/Kconfig: use Cxxx as CPU string for all non-CAR SoCs

Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it
being what the AGESA reference code uses. We initially relied on the
AGESA/FSP generated SSDT for the P- and C-state support before we had a
native implementation for this in coreboot. The Cxxx naming scheme can
also be used for the other AMD SoCs except Stoneyridge which is pre-Zen
and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of
using Cxxx instead of CPxx is that the Cxxx scheme supports systems with
more than 256 CPU threads.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/cpu/Kconfig

@@ -33,6 +33,10 @@ config CBFS_CACHE_SIZE
 	help
 	  The size of the cbfs_cache region.
 
+config ACPI_CPU_STRING
+	string
+	default "\\_SB.C%03d"
+
 endif # SOC_AMD_COMMON_BLOCK_NONCAR
 
 config SOC_AMD_COMMON_BLOCK_MCA_COMMON

src/soc/amd/picasso/Kconfig

@@ -296,10 +296,6 @@ config SMM_MODULE_STACK_SIZE
 	hex
 	default 0x800
 
-config ACPI_CPU_STRING
-	string
-	default "\\_SB.C%03d"
-
 config ACPI_BERT
 	bool "Build ACPI BERT Table"
 	default y