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soc/amd/common/cpu/Kconfig: use Cxxx as CPU string for all non-CAR SoCs 

Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it
being what the AGESA reference code uses. We initially relied on the
AGESA/FSP generated SSDT for the P- and C-state support before we had a
native implementation for this in coreboot. The Cxxx naming scheme can
also be used for the other AMD SoCs except Stoneyridge which is pre-Zen
and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of
using Cxxx instead of CPxx is that the Cxxx scheme supports systems with
more than 256 CPU threads.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-03-04 03:33:54 +01:00
parent bd9dd420d7
commit 649426539b
2 changed files with 4 additions and 4 deletions
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4
src/soc/amd/common/block/cpu/Kconfig
View File

@ -33,6 +33,10 @@ config CBFS_CACHE_SIZE
help help
The size of the cbfs_cache region. The size of the cbfs_cache region.
config ACPI_CPU_STRING
string
default "\\_SB.C%03d"
endif # SOC_AMD_COMMON_BLOCK_NONCAR endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_MCA_COMMON config SOC_AMD_COMMON_BLOCK_MCA_COMMON

4
src/soc/amd/picasso/Kconfig
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@ -296,10 +296,6 @@ config SMM_MODULE_STACK_SIZE
hex hex
default 0x800 default 0x800
config ACPI_CPU_STRING
string
default "\\_SB.C%03d"
config ACPI_BERT config ACPI_BERT
bool "Build ACPI BERT Table" bool "Build ACPI BERT Table"
default y default y