soc/intel/common/acpi: Add IOE PS2B access APIs

This patch implements APIs to access PCR registers from IOE die.

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: Ief7a00c4e81048f87ee308e659faeba3fde4c9cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76409
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/soc/intel/common/acpi/ioe_pcr.asl

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "pcrlib.asl"
+
+/* APIs to access P2SB inside IOE die */
+
+/*
+ * Calculate PCR register base at specified PID
+ * Arg0 - PCR Port ID
+ */
+Method (ICRB, 1, NotSerialized)
+{
+	Return (GPCR(IOE_P2SB, Arg0))
+}
+
+/*
+ * Read a PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ */
+Method (ICRR, 2, Serialized)
+{
+	Return (RPCR(IOE_P2SB, Arg0, Arg1))
+}
+
+/*
+ * AND a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to AND
+ */
+Method (ICRA, 3, Serialized)
+{
+	APCR(IOE_P2SB, Arg0, Arg1, Arg2)
+}
+
+/*
+ * OR a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to OR
+ */
+Method (ICRO, 3, Serialized)
+{
+	OPCR(IOE_P2SB, Arg0, Arg1, Arg2)
+}

src/soc/intel/common/acpi/pcrlib.asl

@@ -8,7 +8,7 @@
 
 /* Die Index */
 #define PCH_P2SB	0x00
-/* TODO: Add index for P2SB which belongs to IOE Die" */
+#define IOE_P2SB	0x01
 
 /*
  * Get PCR register base for specified Die at given PID
@@ -19,10 +19,14 @@ Method (GPCR, 2, NotSerialized)
 {
 	if (Arg0 == PCH_P2SB) {
 		Local0 = CONFIG_PCR_BASE_ADDRESS;
+	} else {
+		if (Arg0 == IOE_P2SB) {
+			Local0 = CONFIG_IOE_PCR_BASE_ADDRESS;
 		} else {
 			Printf ("Invalid Die index (%o)\n", Arg0)
 			Return (0)
 		}
+	}
 
 	Return (Local0 + (Arg1 << PCR_PORTID_SHIFT))
 }