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amd/geode_lx: Remove most boards

Browse source 
There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2018-06-04 06:49:00 +03:00
parent 88af0f38eb
commit 64aa881263
124 changed files with 0 additions and 5844 deletions
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16
src/mainboard/aaeon/Kconfig
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@ -1,16 +0,0 @@
if VENDOR_AAEON
choice
prompt "Mainboard model"
source "src/mainboard/aaeon/*/Kconfig.name"
endchoice
source "src/mainboard/aaeon/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Aaeon"
endif # VENDOR_AAEON

27
src/mainboard/aaeon/pfm-540i_revb/Kconfig
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@ -1,27 +0,0 @@
if BOARD_AAEON_PFM_540I_REVB
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_1024
select POWER_BUTTON_FORCE_ENABLE
config MAINBOARD_DIR
string
default aaeon/pfm-540i_revb
config MAINBOARD_PART_NUMBER
string
default "PFM-540I_REVB"
config IRQ_SLOT_COUNT
int
default 4
endif # BOARD_AAEON_PFM_540I_REVB

2
src/mainboard/aaeon/pfm-540i_revb/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_AAEON_PFM_540I_REVB
bool "PFM-540I_REVB"

3
src/mainboard/aaeon/pfm-540i_revb/board_info.txt
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@ -1,3 +0,0 @@
Board name: PFM-540I Rev.B
Category: half
Board URL: http://www.aaeonusa.com/products/details/?item_id=1043

73
src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
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@ -1,73 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "1" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3E8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2E8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci c.0 on end # ISA Bridge (PC104)
device pci e.0 on end # Ethernet
device pci f.0 on # ISA Bridge
chip superio/smsc/smscsuperio
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 4e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.7 on # Keyboard
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 4e.a off end # Runtime/ACPI
# superio/smsc/smscsuperio currently only supports the first 2 serial ports.
device pnp 4e.b off # Com3
io 0x60 = 0x3e8
irq 0x70 = 10
end
device pnp 4e.c off # Com4
io 0x60 = 0x2e8
irq 0x70 = 11
end
end
end
device pci f.2 on end # IDE Controller
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

70
src/mainboard/aaeon/pfm-540i_revb/irq_tables.c
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@ -1,70 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on irq_tables.c from AMD's DB800 mainboard. */
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 5
#define PIRQB 11
#define PIRQC 10
#define PIRQD 9
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
/* CPU */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
/* Ethernet */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
/* Chipset */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

76
src/mainboard/aaeon/pfm-540i_revb/romstage.c
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@ -1,76 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on romstage.c from AMD's DB800 mainboard. */
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
}

27
src/mainboard/amd/db800/Kconfig
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@ -1,27 +0,0 @@
if BOARD_AMD_DB800
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
config MAINBOARD_DIR
string
default amd/db800
config MAINBOARD_PART_NUMBER
string
default "DB800"
config IRQ_SLOT_COUNT
int
default 4
endif # BOARD_AMD_DB800

2
src/mainboard/amd/db800/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_AMD_DB800
bool "DB800 (Salsa)"

3
src/mainboard/amd/db800/board_info.txt
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@ -1,3 +0,0 @@
Board name: DB800 (Salsa)
Category: eval
Board URL: http://www.amd.com/us/products/embedded/develop-and-design/Pages/development-boards-lx.aspx

28
src/mainboard/amd/db800/cmos.layout
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@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

67
src/mainboard/amd/db800/devicetree.cb
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@ -1,67 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "1" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci d.0 on end # Ethernet
device pci e.0 on end # Slot1
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # Com2
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b off end # HW Monitor
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

65
src/mainboard/amd/db800/irq_tables.c
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@ -1,65 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 10
#define PIRQD 11
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

73
src/mainboard/amd/db800/romstage.c
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@ -1,73 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

27
src/mainboard/amd/f2950/Kconfig
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@ -1,27 +0,0 @@
if BOARD_AMD_F2950
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
config MAINBOARD_DIR
string
default amd/f2950
config MAINBOARD_PART_NUMBER
string
default "F2950"
config IRQ_SLOT_COUNT
int
default 3
endif # BOARD_AMD_F2950

2
src/mainboard/amd/f2950/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_AMD_F2950
bool "F2950"

6
src/mainboard/amd/f2950/board_info.txt
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@ -1,6 +0,0 @@
Board name: F2950
Category: mini
ROM package: PLCC
ROM protocol: LPC
ROM socketed: n
Flashrom support: n

28
src/mainboard/amd/f2950/cmos.layout
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@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

67
src/mainboard/amd/f2950/devicetree.cb
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@ -1,67 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # Integrated cryptoaccelerator
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "1" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci d.0 on end # Ethernet
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # Com2
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b off end # HW Monitor
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

64
src/mainboard/amd/f2950/irq_tables.c
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@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 5
#define PIRQC 10
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

76
src/mainboard/amd/f2950/romstage.c
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@ -1,76 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
return 0xFF;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

26
src/mainboard/amd/norwich/Kconfig
View file

@ -1,26 +0,0 @@
if BOARD_AMD_NORWICH
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
config MAINBOARD_DIR
string
default amd/norwich
config MAINBOARD_PART_NUMBER
string
default "Norwich"
config IRQ_SLOT_COUNT
int
default 6
endif # BOARD_AMD_NORWICH

2
src/mainboard/amd/norwich/Kconfig.name
View file

@ -1,2 +0,0 @@
config BOARD_AMD_NORWICH
bool "Norwich"

1
src/mainboard/amd/norwich/board_info.txt
View file

@ -1 +0,0 @@
Category: eval

29
src/mainboard/amd/norwich/cmos.layout
View file

@ -1,29 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 1 e 0 dcon_present
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

40
src/mainboard/amd/norwich/devicetree.cb
View file

@ -1,40 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
register "lpc_serirq_enable" = "0x00001002"
register "lpc_serirq_polarity" = "0x0000EFFD"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "1"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci b.0 on end # Slot 3
device pci c.0 on end # Slot 4
device pci d.0 on end # Slot 1
device pci e.0 on end # Slot 2
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

67
src/mainboard/amd/norwich/irq_tables.c
View file

@ -1,67 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 5
#define PIRQC 10
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

73
src/mainboard/amd/norwich/romstage.c
View file

@ -1,73 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <northbridge/amd/lx/raminit.h>
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
/* cs5536_disable_internal_uart: disable them for now, set them
* up later...
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

18
src/mainboard/artecgroup/Kconfig
View file

@ -1,18 +0,0 @@
if VENDOR_ARTECGROUP
choice
prompt "Mainboard model"
source "src/mainboard/artecgroup/*/Kconfig.name"
endchoice
config MAINBOARD_VENDOR
string
default "Artec Group"
endif # VENDOR_ARTECGROUP
if VENDOR_ARTECGROUP || VENDOR_LINUTOP
source "src/mainboard/artecgroup/*/Kconfig"
endif # VENDOR_ARTECGROUP || VENDOR_LINUTOP

28
src/mainboard/artecgroup/dbe61/Kconfig
View file

@ -1,28 +0,0 @@
if BOARD_ARTECGROUP_DBE61 || BOARD_LINUTOP_LINUTOP1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_DISABLE
config MAINBOARD_DIR
string
default artecgroup/dbe61
if BOARD_ARTECGROUP_DBE61
config MAINBOARD_PART_NUMBER
string
default "DBE61"
endif
config IRQ_SLOT_COUNT
int
default 3
endif # BOARD_ARTECGROUP_DBE61

2
src/mainboard/artecgroup/dbe61/Kconfig.name
View file

@ -1,2 +0,0 @@
config BOARD_ARTECGROUP_DBE61
bool "DBE61"

3
src/mainboard/artecgroup/dbe61/board_info.txt
View file

@ -1,3 +0,0 @@
Category: settop
Board URL: http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34
Flashrom support: y

28
src/mainboard/artecgroup/dbe61/cmos.layout
View file

@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

41
src/mainboard/artecgroup/dbe61/devicetree.cb
View file

@ -1,41 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
register "lpc_serirq_enable" = "0x00001002"
register "lpc_serirq_polarity" = "0x0000EFFD"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x2F8"
register "com1_irq" = "3"
register "com2_enable" = "1"
register "com2_address" = "0x3F8"
register "com2_irq" = "4"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci b.0 on end # Slot 3
device pci c.0 on end # Slot 4
device pci d.0 on end # Slot 1
device pci e.0 on end # Slot 2
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

64
src/mainboard/artecgroup/dbe61/irq_tables.c
View file

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 10
#define PIRQD 11
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

52
src/mainboard/artecgroup/dbe61/mainboard.c
View file

@ -1,52 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include "southbridge/amd/cs5536/cs5536.h"
static void init_gpio(void)
{
msr_t msr;
printk(BIOS_DEBUG, "Checking GPIO module...\n");
msr = rdmsr(MDD_LBAR_GPIO);
printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
}
static void init(struct device *dev)
{
/* BOARD-SPECIFIC INIT */
printk(BIOS_DEBUG, "ARTECGROUP DBE61 ENTER %s\n", __func__);
init_gpio();
printk(BIOS_DEBUG, "ARTECGROUP DBE61 EXIT %s\n", __func__);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

86
src/mainboard/artecgroup/dbe61/romstage.c
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@ -1,86 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include "spd_table.h"
#include <spd.h>
#include <northbridge/amd/lx/raminit.h>
int spd_read_byte(unsigned int device, unsigned int address)
{
int i;
if (device == DIMM0) {
for (i = 0; i < (ARRAY_SIZE(spd_table)); i++) {
if (spd_table[i].address == address) {
return spd_table[i].data;
}
}
}
/* returns 0xFF on any failures */
return 0xFF;
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
msr_t msr;
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536
*/
/* cs5536_disable_internal_uart disable them. Set them up now... */
cs5536_setup_onchipuart(2); /* dbe61 uses UART2 as COM1 */
/* set address to 3F8 */
msr = rdmsr(MDD_LEG_IO);
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
}

49
src/mainboard/artecgroup/dbe61/spd_table.h
View file

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <spd.h>
struct spd_entry {
unsigned int address;
unsigned int data;
};
/* Save space by using a short list of SPD values used by Geode LX Memory init */
/* 128MB */
const struct spd_entry spd_table [] =
{
{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */
{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */
{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
{SPD_REFRESH, 0x82}, /* Refresh rate/type */
{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */
{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */
{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */
{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */
{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */
{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */
{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */
{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */
{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row active (Trrd) */
{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */
{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width (Tras) */
{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */
{SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal input hold time */
{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
};

16
src/mainboard/bachmann/Kconfig
View file

@ -1,16 +0,0 @@
if VENDOR_BACHMANN
choice
prompt "Mainboard model"
source "src/mainboard/bachmann/*/Kconfig.name"
endchoice
source "src/mainboard/bachmann/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Bachmann electronic"
endif # VENDOR_BACHMANN

34
src/mainboard/bachmann/ot200/Kconfig
View file

@ -1,34 +0,0 @@
if BOARD_BACHMANN_OT200
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_2048
select POWER_BUTTON_DEFAULT_DISABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
config MAINBOARD_DIR
string
default bachmann/ot200
config MAINBOARD_PART_NUMBER
string
default "OT200"
config IRQ_SLOT_COUNT
int
default 6
config PLLMSRlo
hex
default 0x07de001e
endif # BOARD_BACHMANN_OT200

2
src/mainboard/bachmann/ot200/Kconfig.name
View file

@ -1,2 +0,0 @@
config BOARD_BACHMANN_OT200
bool "OT200"

1
src/mainboard/bachmann/ot200/board_info.txt
View file

@ -1 +0,0 @@
Category: settop

2
src/mainboard/bachmann/ot200/cmos.default
View file

@ -1,2 +0,0 @@
boot_option=Fallback
debug_level=Spew

50
src/mainboard/bachmann/ot200/cmos.layout
View file

@ -1,50 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Bachmann electronic GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
entries
# -----------------------------------------------------------------
# RTC reserved
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 2 debug_level
# -----------------------------------------------------------------
# coreboot config options: check sums
1008 16 h 0 check_sum
enumerations
#ID value text
2 0 Emergency
2 1 Alert
2 2 Critical
2 3 Error
2 4 Warning
2 5 Notice
2 6 Info
2 7 Debug
2 8 Spew
4 0 Fallback
4 1 Normal
checksums
checksum 392 1007 1008

40
src/mainboard/bachmann/ot200/devicetree.cb
View file

@ -1,40 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x00000000"
register "lpc_serirq_polarity" = "0x00000000"
register "lpc_serirq_mode" = "0"
register "enable_gpio_int_route" = "0x0C0D0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "1"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "1"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 4.0 on end # Ethernet 0
device pci f.0 on # ISA Bridge
chip drivers/generic/generic # eeprom
device i2c 52 on end
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
device pci f.7 on end # UOC
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

64
src/mainboard/bachmann/ot200/irq_tables.c
View file

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 5
#define PIRQB 9
#define PIRQC 10
#define PIRQD 7
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
0x0f << 3, /* Interrupt router dev */
0, /* IRQs devoted exclusively to PCI usage */
0x100b, /* Vendor */
0x2b, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x20, /* Checksum (has to be set to some value that
* would give 0 after the sum of all bytes
* for this structure (including checksum).
*/
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* ethernet */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

88
src/mainboard/bachmann/ot200/mainboard.c
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@ -1,88 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/smbus.h>
#include <smbios.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <arch/io.h>
/* overwrite a weak function to fill SMBIOS table with a custom value */
static u8 hw_rev = 0;
static char mb_rev_str[2] = { '0' };
const char *smbios_mainboard_version(void)
{
/* UDMA is not working on all supported devices */
if (hw_rev < 113) {
mb_rev_str[0] = '1';
} else {
mb_rev_str[0] = '2';
}
return mb_rev_str;
}
static void init(struct device *dev)
{
unsigned int i;
u32 chksum = 0;
char block[20];
msr_t reset;
device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
if (eeprom_dev == 0) {
printk(BIOS_WARNING, "eeprom not found\n");
return;
}
/* turn off all leds except led_ini */
outb(0x02, 0x5a); /* bit0 - led_run */
/* bit1 - led_ini */
/* bit2 - led_err */
/* bit3-bit7 - write has no effect */
outb(0x00, 0x49); /* bit0-bit6 - led_7-led_1 */
/* bit7 - write has no effect */
/* read the whole block and check if checksum is okay */
for (i = 0; i < 20; i++) {
block[i] = smbus_read_byte(eeprom_dev, i);
chksum += block[i];
}
if (chksum != 0) {
printk(BIOS_WARNING, "wrong checksum: 0x%0x\n", chksum);
}
hw_rev = block[5];
printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev);
/* Reset MFGPT7 (standby power domain) - this is done via
* an undocumented register */
reset = rdmsr(0x5140002b);
reset.lo |= 1 << 7;
wrmsr(0x5140002b, reset);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

74
src/mainboard/bachmann/ot200/romstage.c
View file

@ -1,74 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdlib.h>
#include <stdint.h>
#include <spd.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <northbridge/amd/lx/raminit.h>
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
/* cs5536_disable_internal_uart: disable them for now, set them
* up later...
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

16
src/mainboard/digitallogic/Kconfig
View file

@ -1,16 +0,0 @@
if VENDOR_DIGITALLOGIC
choice
prompt "Mainboard model"
source "src/mainboard/digitallogic/*/Kconfig.name"
endchoice
source "src/mainboard/digitallogic/*/Kconfig"
config MAINBOARD_VENDOR
string
default "DIGITAL-LOGIC"
endif # VENDOR_DIGITALLOGIC

27
src/mainboard/digitallogic/msm800sev/Kconfig
View file

@ -1,27 +0,0 @@
if BOARD_DIGITALLOGIC_MSM800SEV
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
config MAINBOARD_DIR
string
default digitallogic/msm800sev
config MAINBOARD_PART_NUMBER
string
default "MSM800SEV"
config IRQ_SLOT_COUNT
int
default 9
endif # BOARD_DIGITALLOGIC_MSM800SEV

2
src/mainboard/digitallogic/msm800sev/Kconfig.name
View file

@ -1,2 +0,0 @@
config BOARD_DIGITALLOGIC_MSM800SEV
bool "MSM800SEV"

2
src/mainboard/digitallogic/msm800sev/board_info.txt
View file

@ -1,2 +0,0 @@
Category: half
Board URL: http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV

28
src/mainboard/digitallogic/msm800sev/cmos.layout
View file

@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 392 1007 1008

85
src/mainboard/digitallogic/msm800sev/devicetree.cb
View file

@ -1,85 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end
device pci 1.1 on end
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
# How to get these? Boot linux and do this:
# rdmsr 0x51400025
register "lpc_serirq_enable" = "0x0000105a"
# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
register "lpc_serirq_polarity" = "0x0000EFA5"
# mode is high 10 bits (determined from code)
register "lpc_serirq_mode" = "1"
# Don't yet know how to find this.
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci f.1 on end # Flash controller
device pci f.2 on end # IDE controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

71
src/mainboard/digitallogic/msm800sev/irq_tables.c
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@ -1,71 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 5
#define PIRQC 10
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x100b, /* Vendor */
0x2b, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xe, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
{0x00,(0x13 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x12 << 3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x11 << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
{0x00,(0x0a << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
{0x00,(0x0b << 3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
{0x00,(0x0c << 3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
{0x00,(0x0d << 3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

90
src/mainboard/digitallogic/msm800sev/romstage.c
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@ -1,90 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536
*/
cs5536_disable_internal_uart();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Switch from Cache as RAM to real RAM */
/* There are two ways we could think about this.
1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
where LB would like it, you need to write some code to do a copy from cache to RAM
We use method 1 on Norwich.
*/
post_code(0x02);
__asm__("wbinvd\n");
printk(BIOS_ERR, "Past wbinvd\n");
/* we are finding the return does not work on this board. Explicitly call the label that is
* after the call to us. This is gross, but sometimes at this level it is the only way out
*/
done_cache_as_ram_main();
}

32
src/mainboard/iei/pcisa-lx-800-r10/Kconfig
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@ -1,32 +0,0 @@
if BOARD_IEI_PCISA_LX_800_R10
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
default iei/pcisa-lx-800-r10
config MAINBOARD_PART_NUMBER
string
default "PCISA-LX-800-R10"
config IRQ_SLOT_COUNT
int
default 9
config PLLMSRlo
hex
default 0x00DE6000
endif # BOARD_IEI_PCISA_LX_800_R10

2
src/mainboard/iei/pcisa-lx-800-r10/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_IEI_PCISA_LX_800_R10
bool "PCISA LX-800-R10"

2
src/mainboard/iei/pcisa-lx-800-r10/board_info.txt
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@ -1,2 +0,0 @@
Category: half
Board URL: http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX

75
src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
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@ -1,75 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "1" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 9.0 on end # Slot1
device pci a.0 on end # Slot2
device pci b.0 on end # Slot3
device pci c.0 on end # Slot4
device pci e.0 on end # Ethernet 0
device pci 10.0 on end # Ethernet 1
device pci 11.0 on end # SATA
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b off end # HW Monitor
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

292
src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
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@ -1,292 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
// #include <console/console.h>
#include <arch/io.h>
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 10
#define PIRQC 11
#define PIRQD 5
/* Link */
#define LINK_PIRQA 1
#define LINK_PIRQB 2
#define LINK_PIRQC 3
#define LINK_PIRQD 4
#define LINK_NONE 0
/* Map */
#define IRQ_BITMAP_LINKA (1 << PIRQA)
#define IRQ_BITMAP_LINKB (1 << PIRQB)
#define IRQ_BITMAP_LINKC (1 << PIRQC)
#define IRQ_BITMAP_LINKD (1 << PIRQD)
#define IRQ_BITMAP_NOLINK 0x0
#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD)
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */
0x0002, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x62, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
.slots = {
[0] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x01 << 3)|0x0, /* 0x01 is CS5536 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[1] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x0f << 3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQB, /* Audio */
.bitmap = IRQ_BITMAP_LINKB
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQD, /* USB */
.bitmap = IRQ_BITMAP_LINKD
}
}
},
[2] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x0e << 3)|0x0, /* 0x0e is eth0 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[3] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x10 << 3)|0x0, /* 0x10 is eth1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[4] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x11 << 3)|0x0, /* 0x11 is SATA */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
/*
* ################### backplane ###################
*/
/*
* PCI1
*/
[5] = {
.slot = 0x1, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x09 << 3)|0x0, /* 0x09 is PCI1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
}
}
},
/*
* PCI2
*/
[6] = {
.slot = 0x2, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0a << 3)|0x0, /* 0x0a is PCI2 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
}
}
},
/*
* PCI3
*/
[7] = {
.slot = 0x3, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0b << 3)|0x0, /* 0x0b is PCI3 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
}
}
},
/*
* PCI4
*/
[8] = {
.slot = 0x4, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0c << 3)|0x0, /* 0x0c is PCI4 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
}
}
},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
/* Put the PIR table in memory and checksum. */
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

73
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
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@ -1,73 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
}

48
src/mainboard/iei/pm-lx-800-r11/Kconfig
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@ -1,48 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_IEI_PM_LX_800_R11
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627EHG
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
default iei/pm-lx-800-r11
config MAINBOARD_PART_NUMBER
string
default "PM-LX-800-R11"
config IRQ_SLOT_COUNT
int
default 7
config PLLMSRlo
hex
default 0x07de0000
endif # BOARD_IEI_PM_LX_800_R11

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src/mainboard/iei/pm-lx-800-r11/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_IEI_PM_LX_800_R11
bool "PM LX-800-R11"

6
src/mainboard/iei/pm-lx-800-r11/board_info.txt
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@ -1,6 +0,0 @@
Category: half
Board URL: http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110#.UCLx8cLlgao
ROM package: PLCC
ROM protocol: LPC
ROM socketed: y
Flashrom support: y

96
src/mainboard/iei/pm-lx-800-r11/devicetree.cb
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@ -1,96 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x0000115a"
register "lpc_serirq_polarity" = "0x0000eea5"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0d0c0700"
register "enable_ide_nand_flash" = "0"
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0"
register "com1_enable" = "1" # CN10 (RS422/486 COM3)
register "com1_address" = "0x3e8"
register "com1_irq" = "5"
register "com2_enable" = "0"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci e.0 on end # RTL8100C
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627ehg # Winbond W83627EHG
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 keyboard/mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.6 off end # Serial Flash Interface
device pnp 2e.7 off end # GPIO1, GPIO6, Game Port & MIDI Port
device pnp 2e.8 off end # WDTO# & PLED
device pnp 2e.9 off end # GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED
device pnp 2e.a off end # ACPI
device pnp 2e.106 off end #
device pnp 2e.107 off end #
device pnp 2e.207 off end #
end
end
device pci f.2 on end # IDE Controller
device pci f.3 off end # Audio (N/A)
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

224
src/mainboard/iei/pm-lx-800-r11/irq_tables.c
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@ -1,224 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ids.h>
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 11
#define PIRQD 11
/* Links */
#define L_PIRQA 1
#define L_PIRQB 2
#define L_PIRQC 3
#define L_PIRQD 4
/* Bitmaps */
#define B_LINK0 (1 << PIRQA)
#define B_LINK1 (1 << PIRQB)
#define B_LINK2 (1 << PIRQC)
#define B_LINK3 (1 << PIRQD)
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
0x0f << 3, /* Interrupt router dev */
B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3, /* IRQs devoted exclusively to PCI usage */
PCI_VENDOR_ID_AMD, /* Vendor */
PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
0, /* Miniport */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* Reserved */
0xa6, /* Checksum */
{
[0] = { /* Host bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x01 << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[1] = { /* ISA bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0f << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[2] = { /* Ethernet */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0e << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[1] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[2] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[3] = {
.link = L_PIRQC,
.bitmap = B_LINK2
}
}
},
[3] = { /* PCI Connector - Slot 0 */
.slot = 0x01,
.bus = 0x00,
.devfn = (0x09 << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[4] = { /* PCI Connector - Slot 1 */
.slot = 0x02,
.bus = 0x00,
.devfn = (0x0c << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[1] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[2] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[3] = {
.link = L_PIRQA,
.bitmap = B_LINK0
}
}
},
[5] = { /* PCI Connector - Slot 2 */
.slot = 0x03,
.bus = 0x00,
.devfn = (0x0b << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQC,
.bitmap = B_LINK2
},
[1] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[2] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[3] = {
.link = L_PIRQB,
.bitmap = B_LINK1
}
}
},
[6] = { /* PCI Connector - Slot 3 */
.slot = 0x04,
.bus = 0x00,
.devfn = (0x0a << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[1] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[2] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[3] = {
.link = L_PIRQC,
.bitmap = B_LINK2
}
}
}
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

69
src/mainboard/iei/pm-lx-800-r11/romstage.c
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@ -1,69 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdlib.h>
#include <spd.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
/* Only DIMM0 is available. */
if (device != DIMM0)
return 0xff;
return smbus_read_byte(device, address);
}
#include <northbridge/amd/lx/pll_reset.c>
#include <cpu/amd/geode_lx/cpureginit.c>
#include <cpu/amd/geode_lx/syspreinit.c>
#include <cpu/amd/geode_lx/msrinit.c>
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
}

48
src/mainboard/iei/pm-lx2-800-r10/Kconfig
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@ -1,48 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_IEI_PM_LX2_800_R10
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
default iei/pm-lx2-800-r10
config MAINBOARD_PART_NUMBER
string
default "PM-LX2-800-R10"
config IRQ_SLOT_COUNT
int
default 3
config PLLMSRlo
hex
default 0x07de0000
endif # BOARD_IEI_PM_LX2_800_R10

2
src/mainboard/iei/pm-lx2-800-r10/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_IEI_PM_LX2_800_R10
bool "PM LX2-800-R10"

6
src/mainboard/iei/pm-lx2-800-r10/board_info.txt
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@ -1,6 +0,0 @@
Category: half
Board URL: http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=09034367569861123956#.UI2CfiExUao
ROM package: PLCC
ROM protocol: LPC
ROM socketed: y
Flashrom support: y

82
src/mainboard/iei/pm-lx2-800-r10/devicetree.cb
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@ -1,82 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x000010da"
register "lpc_serirq_polarity" = "0x0000ef25"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0d0c0700"
register "enable_ide_nand_flash" = "0"
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0"
register "com1_enable" = "0"
register "com2_enable" = "0"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 11.0 on end # IT8888
device pci e.0 on end # RTL8100C
device pci f.0 on # ISA Bridge
chip superio/smsc/smscsuperio # SMSC SCH3114
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # PS/2 keyboard/mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.a on # Runtime Register
io 0x60 = 0x400
end
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

130
src/mainboard/iei/pm-lx2-800-r10/irq_tables.c
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@ -1,130 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ids.h>
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 10
#define PIRQC 11
#define PIRQD 11
/* Links */
#define L_PIRQN 0
#define L_PIRQA 1
#define L_PIRQB 2
#define L_PIRQC 3
#define L_PIRQD 4
/* Bitmaps */
#define B_LINKN (0)
#define B_LINK0 (1 << PIRQA)
#define B_LINK1 (1 << PIRQB)
#define B_LINK2 (1 << PIRQC)
#define B_LINK3 (1 << PIRQD)
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x0f << 3) | 0x0, /* Interrupt router dev */
(B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */
PCI_VENDOR_ID_AMD, /* Vendor */
PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
0, /* Miniport */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
0x27, /* Checksum */
{
[0] = { /* Host bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x01 << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQA,
.bitmap = B_LINK0
},
[1] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[2] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[3] = {
.link = L_PIRQN,
.bitmap = B_LINKN
}
}
},
[1] = { /* ISA bridge */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0f << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[1] = {
.link = L_PIRQB,
.bitmap = B_LINK1
},
[2] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[3] = {
.link = L_PIRQD,
.bitmap = B_LINK3
}
}
},
[2] = { /* Ethernet */
.slot = 0x00,
.bus = 0x00,
.devfn = (0x0e << 3) | 0x0,
.irq = {
[0] = {
.link = L_PIRQD,
.bitmap = B_LINK3
},
[1] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[2] = {
.link = L_PIRQN,
.bitmap = B_LINKN
},
[3] = {
.link = L_PIRQN,
.bitmap = B_LINKN
}
}
}
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

47
src/mainboard/iei/pm-lx2-800-r10/mainboard.c
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@ -1,47 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/device.h>
#include <boot/tables.h>
/* SCH3114 runtime register (RTR) address. */
#define SCH3114_RTR_ADDR (0x400)
/* H/W Monitoring register block index. */
#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70)
/* H/W Monitoring register block data. */
#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71)
/* H/W Monitoring Ready/Lock/Start register. */
#define SCH3114_HWM_RLS_REG (0x40)
static void init(struct device *dev)
{
/* SCH3114: enable hardware monitor. */
printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n");
outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX);
outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

81
src/mainboard/iei/pm-lx2-800-r10/romstage.c
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@ -1,81 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <spd.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
int spd_read_byte(unsigned int device, unsigned int address)
{
/* Only DIMM0 is available. */
if (device != DIMM0)
return 0xFF;
return smbus_read_byte(device, address);
}
#include <northbridge/amd/lx/pll_reset.c>
#include <cpu/amd/geode_lx/cpureginit.c>
#include <cpu/amd/geode_lx/syspreinit.c>
#include <cpu/amd/geode_lx/msrinit.c>
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Enable COM3. */
pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b);
u16 port = dev >> 8;
outb(0x55, port);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
outb(0xaa, port);
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
}

16
src/mainboard/linutop/Kconfig
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@ -1,16 +0,0 @@
if VENDOR_LINUTOP
choice
prompt "Mainboard model"
source "src/mainboard/linutop/*/Kconfig.name"
endchoice
config MAINBOARD_VENDOR
string
default "Linutop"
source "src/mainboard/linutop/*/Kconfig"
endif # VENDOR_LINUTOP

2
src/mainboard/linutop/Kconfig.name
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@ -1,2 +0,0 @@
config VENDOR_LINUTOP
bool "Linutop"

9
src/mainboard/linutop/linutop1/Kconfig
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@ -1,9 +0,0 @@
if BOARD_LINUTOP_LINUTOP1
# Dummy for abuild
config MAINBOARD_PART_NUMBER
string
default "Linutop-1"
endif

2
src/mainboard/linutop/linutop1/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_LINUTOP_LINUTOP1
bool "Linutop-1"

4
src/mainboard/linutop/linutop1/board_info.txt
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@ -1,4 +0,0 @@
Category: settop
Board URL: http://www.linutop.com
Flashrom support: y
Clone of: artecgroup/dbe61

56
src/mainboard/lippert/hurricane-lx/Kconfig
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@ -1,56 +0,0 @@
if BOARD_LIPPERT_HURRICANE_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_ITE_IT8712F
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_333
select POWER_BUTTON_FORCE_ENABLE if !BOARD_OLD_REVISION
config MAINBOARD_DIR
string
default lippert/hurricane-lx
config MAINBOARD_PART_NUMBER
string
default "Hurricane-LX"
config IRQ_SLOT_COUNT
int
default 8
config BOARD_OLD_REVISION
bool "Board is old pre-3.0 revision"
default n
select POWER_BUTTON_DEFAULT_DISABLE
help
Look on the bottom side for a number like 406-0001-30. The last 2
digits state the PCB revision (3.0 in this example). For 2.0 or older
boards choose Y, for 3.0 and newer say N.
Old revision boards need a jumper shorting the power button to
power on automatically. You may enable the button only after this
jumper has been removed. New revision boards are not restricted
in this way, and always have the power button enabled.
config ONBOARD_UARTS_RS485
bool "Switch on-board serial ports to RS485"
default n
help
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_HURRICANE_LX

2
src/mainboard/lippert/hurricane-lx/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_LIPPERT_HURRICANE_LX
bool "Hurricane-LX"

6
src/mainboard/lippert/hurricane-lx/board_info.txt
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@ -1,6 +0,0 @@
Category: half
Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1154
ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: n

90
src/mainboard/lippert/hurricane-lx/devicetree.cb
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@ -1,90 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
# UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3E8"
register "com1_irq" = "6"
register "com2_enable" = "0"
register "com2_address" = "0x2E8"
register "com2_irq" = "6"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 8.0 on end # Slot4
device pci 9.0 on end # Slot3
device pci a.0 on end # Slot2
device pci b.0 on end # Slot1
device pci c.0 on end # IT8888
device pci d.0 on end # Mini-PCI
device pci e.0 on end # Ethernet
device pci f.0 on # ISA Bridge
chip superio/ite/it8712f
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # EC
io 0x60 = 0x290 # EC
io 0x62 = 0x298 # PME
irq 0x70 = 9
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 on # PS/2 mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
io 0x62 = 0x1220 # Simple I/O
io 0x64 = 0x1228 # SPI
end
device pnp 2e.8 off # MIDI
io 0x60 = 0x300
irq 0x70 = 9
end
device pnp 2e.9 off # Game port
io 0x60 = 0x220
end
device pnp 2e.a off end # CIR
end
end
device pci f.2 on end # IDE
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

72
src/mainboard/lippert/hurricane-lx/irq_tables.c
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@ -1,72 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on irq_tables.c from the SpaceRunner-LX mainboard. */
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 5
#define PIRQD 15
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x36, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */
{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */
{0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */
{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x5, 0x0}, /* Mini-PCI */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

83
src/mainboard/lippert/hurricane-lx/mainboard.c
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@ -1,83 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
#include <stdlib.h>
#include <stdint.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x06
#else
#define SIO_GP1X_CONFIG 0x00
#endif
static const u16 ec_init_table[] = { /* hi = data, lo = index */
0x1900, /* Enable monitoring */
0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
0x805C, /* Unlock zero adjust */
0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
0x005C, /* Lock zero adjust */
0xD014 /* Also set FAN_CTL polarity to Active High */
};
static void init(struct device *dev)
{
unsigned int gpio_base, i;
printk(BIOS_DEBUG, "LiPPERT Hurricane-LX ENTER %s\n", __func__);
/* Init CS5536 GPIOs */
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
outl(0x00000040, gpio_base + 0x08); // GPIO6 open drain 1 - LAN_PD# (jumpered GPIO per default)
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
#endif
outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old)
/* Init Environment Controller. */
for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
u16 val = ec_init_table[i];
outb((u8)val, 0x0295);
outb(val >> 8, 0x0296);
}
/* bit2 = RS485_EN2, bit1 = RS485_EN1 */
outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
printk(BIOS_DEBUG, "LiPPERT Hurricane-LX EXIT %s\n", __func__);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

144
src/mainboard/lippert/hurricane-lx/romstage.c
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@ -1,144 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on romstage.c from the SpaceRunner-LX mainboard. */
#include <stdlib.h>
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <southbridge/amd/cs5536/smbus.h>
#include <spd.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum. */
#define SMC_CONFIG 0x01
int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
return smbus_read_byte(device, address);
}
#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
/* Send config data to System Management Controller via SMB. */
static int smc_send_config(unsigned char config_data)
{
if (smbus_check_stop_condition(SMBUS_IO_BASE))
return 1;
if (smbus_start_condition(SMBUS_IO_BASE))
return 2;
if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
return 3;
if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
return 4;
if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
return 5;
if (smbus_send_command(SMBUS_IO_BASE, config_data))
return 6;
smbus_stop_condition(SMBUS_IO_BASE);
return 0;
}
#endif
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi = data, lo = index
0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
#endif
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
0xBF27, 0xFF28, 0x2D29, // (GP36 = FAN_CTL3 (PWM), GP23,22,16,15 = SPI, GP13 = PWROK1)
0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN
0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE
0x06C8, // config GP12,11 as output, GP10 as input
0x2DF5, // map Hw Monitor Thermal Output to GP55
#if IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
0x1F2A, 0xC072, // switch GP13 to GPIO, WDT output from PWROK to KRST
#endif
};
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
int i;
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 reg = sio_init_table[i];
ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
}
}
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/*
* Note: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
int err;
/* bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {
printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
}
#endif
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
}

50
src/mainboard/lippert/literunner-lx/Kconfig
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@ -1,50 +0,0 @@
if BOARD_LIPPERT_LITERUNNER_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_ITE_IT8712F
select HAVE_DEBUG_SMBUS
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_400
config MAINBOARD_DIR
string
default lippert/literunner-lx
config MAINBOARD_PART_NUMBER
string
default "Cool LiteRunner-LX"
config IRQ_SLOT_COUNT
int
default 5
config ONBOARD_UARTS_RS485
bool "Switch on-board serial ports 1 & 2 to RS485"
default n
help
If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.
config ONBOARD_IDE_SLAVE
bool "Make on-board CF socket act as Slave"
default n
help
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_LITERUNNER_LX

2
src/mainboard/lippert/literunner-lx/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_LIPPERT_LITERUNNER_LX
bool "Cool LiteRunner-LX"

6
src/mainboard/lippert/literunner-lx/board_info.txt
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@ -1,6 +0,0 @@
Category: half
Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1128
ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: n

87
src/mainboard/lippert/literunner-lx/devicetree.cb
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@ -1,87 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
# UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000129A" # 00010010 10011010
register "lpc_serirq_polarity" = "0x0000ED65" # inverse of above
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "1"
register "com1_address" = "0x3E8"
register "com1_irq" = "6"
register "com2_enable" = "0"
register "com2_address" = "0x2E8"
register "com2_irq" = "6"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 8.0 on end # Ethernet 2
device pci c.0 on end # IT8888
device pci d.0 on end # Mini-PCI
device pci e.0 on end # Ethernet 1
device pci f.0 on # ISA Bridge
chip superio/ite/it8712f
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # EC
io 0x60 = 0x290 # EC
io 0x62 = 0x298 # PME
irq 0x70 = 9
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 on # PS/2 mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
io 0x62 = 0x1220 # Simple I/O
io 0x64 = 0x1228 # SPI
end
device pnp 2e.8 off # MIDI
io 0x60 = 0x300
irq 0x70 = 9
end
device pnp 2e.9 off # Game port
io 0x60 = 0x220
end
device pnp 2e.a off end # CIR
end
end
device pci f.2 on end # IDE
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

69
src/mainboard/lippert/literunner-lx/irq_tables.c
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@ -1,69 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on irq_tables.c from the SpaceRunner-LX mainboard. */
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 5
#define PIRQD 15
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0xB8, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1 */
{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2 */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* Mini-PCI */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

87
src/mainboard/lippert/literunner-lx/mainboard.c
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@ -1,87 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
#include <stdlib.h>
#include <stdint.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x07
#else
#define SIO_GP1X_CONFIG 0x01
#endif
/* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */
#define SIO_GP2X_CONFIG 0x00
static const u16 ec_init_table[] = { /* hi = data, lo = index */
0x1900, /* Enable monitoring */
0x3050, /* VIN4,5 enabled */
0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
0x805C, /* Unlock zero adjust */
0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
0x005C, /* Lock zero adjust */
0xD014 /* Also set FAN_CTL polarity to Active High */
};
static void init(struct device *dev)
{
unsigned int gpio_base, i;
printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX ENTER %s\n", __func__);
/* Init CS5536 GPIOs */
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
/* Init Environment Controller. */
for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
u16 val = ec_init_table[i];
outb((u8)val, 0x0295);
outb(val >> 8, 0x0296);
}
/* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
/* bit1 = COM3_RX_EN, bit0 = COM3_TX_EN */
outb(SIO_GP2X_CONFIG, 0x1221); /* Simple-I/O GP27-20 */
printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX EXIT %s\n", __func__);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

182
src/mainboard/lippert/literunner-lx/romstage.c
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@ -1,182 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on romstage.c from the SpaceRunner-LX mainboard. */
#include <stdlib.h>
#include <stdint.h>
#include <spd.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <southbridge/amd/cs5536/smbus.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE)
#define SMC_CONFIG 0x03
#else
#define SMC_CONFIG 0x01
#endif
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
[SPD_NUM_ROWS] = 0x0D, // Number of row address bits [13]
[SPD_NUM_COLUMNS] = 0x0A, // Number of column address bits [10]
[SPD_NUM_DIMM_BANKS] = 1, // Number of module rows (banks)
0xFF, 0xFF, 0xFF,
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x50, // SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [5.0 ns in BCD]
0xFF, 0xFF,
[SPD_REFRESH] = 0x82, // Refresh rate/type [Self Refresh, 7.8 us]
[SPD_PRIMARY_SDRAM_WIDTH] = 64, // SDRAM width (primary SDRAM) [64 bits]
0xFF, 0xFF, 0xFF,
[SPD_NUM_BANKS_PER_SDRAM] = 4, // SDRAM device attributes, number of banks on SDRAM device
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, // SDRAM device attributes, CAS latency [3, 2.5, 2]
0xFF, 0xFF,
[SPD_MODULE_ATTRIBUTES] = 0x20, // SDRAM module attributes [differential clk]
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, // SDRAM device attributes, general [Concurrent AP]
[SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, // SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD]
0xFF,
[SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, // SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD]
0xFF,
[SPD_tRP] = 60, // Min. row precharge time [15 ns in units of 0.25 ns]
[SPD_tRRD] = 40, // Min. row active to row active [10 ns in units of 0.25 ns]
[SPD_tRCD] = 60, // Min. RAS to CAS delay [15 ns in units of 0.25 ns]
[SPD_tRAS] = 40, // Min. RAS pulse width = active to precharge delay [40 ns]
[SPD_BANK_DENSITY] = 0x40, // Density of each row on module [256 MB]
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
[SPD_tRFC] = 70 // SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [70 ns]
};
int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF)
printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
"returns 0xff\n", address);
#endif
/* Fake SPD ROM value */
return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
}
/* Send config data to System Management Controller via SMB. */
static int smc_send_config(unsigned char config_data)
{
if (smbus_check_stop_condition(SMBUS_IO_BASE))
return 1;
if (smbus_start_condition(SMBUS_IO_BASE))
return 2;
if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
return 3;
if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
return 4;
if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
return 5;
if (smbus_send_command(SMBUS_IO_BASE, config_data))
return 6;
smbus_stop_condition(SMBUS_IO_BASE);
return 0;
}
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi = data, lo = index
0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
#endif
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
0xFF27, 0xDF28, 0x2729, // (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1)
0x66B8, 0x0FB9, // enable pullups on SPI, RS485_EN, COM3_R/TX_EN
0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
0x03C1, // enable Simple-I/O for GP21-20= COM3_RX_EN,TX_EN
0xFFC2, // enable Simple-I/O for GP37-30
0x07C8, // config GP12-10 as output
0x03C9, // config GP21-20 as output
0x2DF5, // map Hw Monitor Thermal Output to GP55
0x08F8, // map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use)
};
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
int i;
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 reg = sio_init_table[i];
ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
}
}
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
int err;
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/*
* Note: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {
printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
}
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
}

42
src/mainboard/lippert/roadrunner-lx/Kconfig
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@ -1,42 +0,0 @@
if BOARD_LIPPERT_ROADRUNNER_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_ITE_IT8712F
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
# Standard chip is a 512 KB FWH. Replacing it with a 1 MB
# SST 49LF008A is possible.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_333
config MAINBOARD_DIR
string
default lippert/roadrunner-lx
config MAINBOARD_PART_NUMBER
string
default "Cool RoadRunner-LX"
config IRQ_SLOT_COUNT
int
default 7
config ONBOARD_UARTS_RS485
bool "Switch on-board serial ports to RS485"
default n
help
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_ROADRUNNER_LX

2
src/mainboard/lippert/roadrunner-lx/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_LIPPERT_ROADRUNNER_LX
bool "Cool RoadRunner-LX"

6
src/mainboard/lippert/roadrunner-lx/board_info.txt
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@ -1,6 +0,0 @@
Category: half
Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1147
ROM package: PLCC
ROM protocol: FWH
ROM socketed: y
Flashrom support: y

89
src/mainboard/lippert/roadrunner-lx/devicetree.cb
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@ -1,89 +0,0 @@
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536 # Southbridge
# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power...
# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
# UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3E8"
register "com1_irq" = "6"
register "com2_enable" = "0"
register "com2_address" = "0x2E8"
register "com2_irq" = "6"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 8.0 on end # Slot4
device pci 9.0 on end # Slot3
device pci a.0 on end # Slot2
device pci b.0 on end # Slot1
device pci c.0 on end # IT8888
device pci e.0 on end # Ethernet
device pci f.0 on # ISA bridge
chip superio/ite/it8712f
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # EC
io 0x60 = 0x290 # EC
io 0x62 = 0x298 # PME
irq 0x70 = 9
end
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 on # PS/2 mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
io 0x62 = 0x1220 # Simple I/O
# io 0x64 = 0x1228 # SPI
end
device pnp 2e.8 off # MIDI
io 0x60 = 0x300
irq 0x70 = 9
end
device pnp 2e.9 off # Game port
io 0x60 = 0x220
end
device pnp 2e.a off end # CIR
end
end
device pci f.2 on end # IDE controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

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src/mainboard/lippert/roadrunner-lx/irq_tables.c
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@ -1,71 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on irq_tables.c from AMD's DB800 mainboard. */
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
#define PIRQA 10
#define PIRQB 11
#define PIRQC 5
#define PIRQD 15
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */
0x002B, /* Device */
0, /* Miniport data */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */
{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */
{0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */
{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

77
src/mainboard/lippert/roadrunner-lx/mainboard.c
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@ -1,77 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Based on mainboard.c from AMD's DB800 mainboard. */
#include <stdlib.h>
#include <stdint.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x26
#else
#define SIO_GP1X_CONFIG 0x20
#endif
static const u16 ec_init_table[] = { /* hi = data, lo = index */
0x1900, /* Enable monitoring */
0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
0x805C, /* Unlock zero adjust */
0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
0x005C, /* Lock zero adjust */
0xD014 /* Also set FAN_CTL polarity to Active High */
};
static void init(struct device *dev)
{
unsigned int gpio_base, i;
printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX ENTER %s\n", __func__);
/* Init CS5536 GPIOs. */
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED
/* Init Environment Controller. */
for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
u16 val = ec_init_table[i];
outb((u8)val, 0x0295);
outb(val >> 8, 0x0296);
}
/* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */
outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX EXIT %s\n", __func__);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

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