Updated.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
8cff29d63e
commit
64b2e474b1
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@ -29,8 +29,8 @@
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#include <types.h>
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#include <arch/io.h>
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#include <pci.h>
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#include <printk.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include "w83c553f.h"
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#ifndef CONFIG_ISA_MEM
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@ -54,6 +54,7 @@ void initialise_dma(void);
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extern struct pci_ops pci_direct_ppc;
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#if 0
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void southbridge_early_init(void)
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{
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unsigned char reg8;
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@ -67,16 +68,17 @@ void southbridge_early_init(void)
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, ®8);
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}
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#endif
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void southbridge_init(void)
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{
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struct pci_dev *devbusfn;
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struct device *dev;
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unsigned char reg8;
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unsigned short reg16;
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unsigned int reg32;
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
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if (devbusfn == 0)
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dev = dev_find_device(W83C553F_VID, W83C553F_DID, 0);
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if (dev == 0)
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{
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printk_info("Error: Cannot find W83C553F controller on any PCI bus\n");
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return;
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@ -86,47 +88,47 @@ void southbridge_init(void)
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/* always enabled */
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#if 0
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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pci_write_config16(dev, PCI_COMMAND, reg16);
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#endif
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/*
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* Set ISA memory space
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*/
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pci_read_config_byte(devbusfn, W83C553F_IPADCR, ®8);
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reg8 = pci_read_config8(dev, W83C553F_IPADCR);
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/* 16 MB ISA memory space */
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_write_config_byte(devbusfn, W83C553F_IPADCR, reg8);
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pci_write_config8(dev, W83C553F_IPADCR, reg8);
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/*
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* Chip select: switch off BIOS write protection
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*/
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pci_read_config_byte(devbusfn, W83C553F_CSCR, ®8);
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reg8 = pci_read_config8(dev, W83C553F_CSCR);
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reg8 |= W83C553F_CSCR_UBIOSCSE;
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reg8 &= ~W83C553F_CSCR_BIOSWP;
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pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8);
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pci_write_config8(dev, W83C553F_CSCR, reg8);
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/*
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* Enable Port 92
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*/
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reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
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pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8);
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pci_write_config8(dev, W83C553F_CSCR, reg8);
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/*
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* Route IDE interrupts to IRQ 14 & 15 on 8259.
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*/
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pci_write_config_byte(devbusfn, W83C553F_IDEIRCR, 0xef);
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pci_write_config_word(devbusfn, W83C553F_PCIIRCR, 0x0000);
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pci_write_config8(dev, W83C553F_IDEIRCR, 0xef);
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pci_write_config16(dev, W83C553F_PCIIRCR, 0x0000);
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/*
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* Read IDE bus offsets from function 1 device.
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* We must unmask the LSB indicating that it is an IO address.
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*/
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_IDE, 0);
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if (devbusfn == 0)
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dev = dev_find_device(W83C553F_VID, W83C553F_IDE, 0);
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if (dev == 0)
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{
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printk_info("Error: Cannot find W83C553F function 1 device\n");
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return;
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@ -136,47 +138,46 @@ void southbridge_init(void)
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* Enable native mode on IDE ports and set base address.
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*/
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reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
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pci_write_config_byte(devbusfn, W83C553F_PIR, reg8);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0x1f0);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0x3f6);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0x170);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0x376);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32);
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pci_write_config8(dev, W83C553F_PIR, reg8);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0x1f0);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x3f6);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
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pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0x170);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
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pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
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pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0x376);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
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/*
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* Set read-ahead duration to 0xff
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* Enable P0 and P1
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*/
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reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
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pci_write_config_dword(devbusfn, W83C553F_IDECSR, reg32);
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pci_read_config_dword(devbusfn, W83C553F_IDECSR, ®32);
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pci_write_config32(dev, W83C553F_IDECSR, reg32);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
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ide_bus_offset[0] = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]);
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ide_bus_offset[0] &= ~1;
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#if CONFIG_IDE_MAXBUS > 1
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
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ide_bus_offset[1] = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
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ide_bus_offset[1] &= ~1;
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#endif
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/*
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* Enable function 1, IDE -> busmastering and IO space access
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*/
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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pci_write_config16(dev, PCI_COMMAND, reg16);
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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/*
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* Initialise ISA interrupt controller
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