mb/google/brya/variant/taeko: Update memory settings
Based on the Taeko's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Joey Peng
Tim Wawrzynczak
parent
3c8dc63457
commit
64be788420
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@ -1,3 +1,5 @@
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bootblock-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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@ -0,0 +1,97 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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static const struct mb_cfg baseboard_memcfg = {
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.type = MEM_TYPE_LP4X,
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.rcomp = {
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/* Baseboard uses only 100ohm Rcomp resistors */
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.resistor = 100,
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/* Baseboard Rcomp target values */
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.targets = {40, 30, 30, 30, 30},
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},
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/* DQ byte map */
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.lpx_dq_map = {
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.ddr0 = {
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.dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, },
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.dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, },
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},
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.ddr1 = {
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.dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, },
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.dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, },
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},
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.ddr2 = {
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.dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, },
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.dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, },
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},
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.ddr3 = {
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.dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, },
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.dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, },
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},
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.ddr4 = {
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.dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, },
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.dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, },
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},
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.ddr5 = {
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.dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, },
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.dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, },
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},
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.ddr6 = {
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.dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, },
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.dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, },
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},
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.ddr7 = {
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.dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, },
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.dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, },
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},
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},
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/* DQS CPU<>DRAM map */
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.lpx_dqs_map = {
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.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
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},
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.ect = 1, /* Enable Early Command Training */
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};
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const struct mb_cfg *__weak variant_memory_params(void)
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{
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return &baseboard_memcfg;
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}
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int __weak variant_memory_sku(void)
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{
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/*
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* Memory configuration board straps
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* GPIO_MEM_CONFIG_0 GPP_E11
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* GPIO_MEM_CONFIG_1 GPP_E2
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* GPIO_MEM_CONFIG_2 GPP_E1
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* GPIO_MEM_CONFIG_3 GPP_E12
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*/
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gpio_t spd_gpios[] = {
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GPP_E11,
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GPP_E2,
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GPP_E1,
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GPP_E12,
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};
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return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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}
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bool __weak variant_is_half_populated(void)
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{
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/* GPIO_MEM_CH_SEL GPP_E13 */
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return gpio_get(GPP_E13);
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}
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@ -1,5 +1,5 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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## This is an auto-generated file. Do not edit!!
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## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
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SPD_SOURCES = placeholder.spd.hex
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SPD_SOURCES =
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SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267
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@ -1 +1,7 @@
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DRAM Part Name ID to assign
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MT53E512M32D2NP-046 WT:E 0 (0000)
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K4U6E3S4AA-MGCR 0 (0000)
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H9HCNNNBKMMLXR-NEE 0 (0000)
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MT53E512M32D1NP-046 WT:B 0 (0000)
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K4U6E3S4AB-MGCL 0 (0000)
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H54G46CYRBX267 0 (0000)
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@ -1,11 +1,6 @@
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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# Only include a fixed ID if it is required for legacy reasons!
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# Generated IDs are dependent on the order of parts in this file,
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# so new parts must always be added at the end of the file!
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#
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# Generate an updated Makefile.inc and dram_id.generated.txt by running the
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# gen_part_id tool from util/spd_tools/lp4x.
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# See util/spd_tools/lp4x/README.md for more details and instructions.
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# Part Name
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MT53E512M32D2NP-046 WT:E
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K4U6E3S4AA-MGCR
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H9HCNNNBKMMLXR-NEE
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MT53E512M32D1NP-046 WT:B
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K4U6E3S4AB-MGCL
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H54G46CYRBX267
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