diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 89f6aaf191..7453eb0222 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -35,9 +35,10 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
 			continue;
 		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
 			continue;
-		/* flags 0 means, RP config is not specify from devicetree */
-		if (cfg[i].flags == 0)
+		if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
+			printk(BIOS_WARNING, "Missing root port clock structure definition\n");
 			continue;
+		}
 		if (clk_req_mapping & (1 << cfg[i].clk_req))
 			printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
 				, cfg[i].clk_req);