mediatek/mt8183: Add md power-off flow

SRCCLKENA holds 26M clock, which will fail suspend/resume,
and the SRCCLKENA is not used by mt8183,
so we can simply release it for suspend/resume to work.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui, suspend test pass.

Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082
Signed-off-by: Yanjie.jiang <yanjie.jiang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32666
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/mt8183/Makefile.inc

@@ -54,6 +54,7 @@ ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/usb.c
 ramstage-y += ../common/wdt.c
+ramstage-y += md_ctrl.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include

src/soc/mediatek/mt8183/include/soc/md_ctrl.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_MEDIATEK_MD_CTRL_H__
+#define __SOC_MEDIATEK_MD_CTRL_H__
+
+void mtk_md_early_init(void);
+
+#endif

src/soc/mediatek/mt8183/md_ctrl.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/infracfg.h>
+#include <soc/pll.h>
+#include <soc/md_ctrl.h>
+
+#define TOPCKGEN_CLK_MODE_MD_32K     (1 << 8)
+#define TOPCKGEN_CLK_MODE_MD_26M     (1 << 9)
+#define INFRA_MISC2_SRCCLKENA_RELEASE (0xFF)
+
+static void internal_md_power_down(void)
+{
+	/* Gating MD clock */
+	setbits_le32(&mtk_topckgen->clk_mode,
+		TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M);
+	/* Release SRCCLKENA */
+	clrbits_le32(&mt8183_infracfg->infra_misc2,
+		INFRA_MISC2_SRCCLKENA_RELEASE);
+}
+
+void mtk_md_early_init(void)
+{
+	internal_md_power_down();
+}

src/soc/mediatek/mt8183/soc.c

@@ -15,10 +15,10 @@
 
 #include <device/device.h>
 #include <soc/emi.h>
+#include <soc/md_ctrl.h>
 #include <soc/mmu_operations.h>
 #include <symbols.h>
 
-
 static void soc_read_resources(struct device *dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
@@ -27,6 +27,7 @@ static void soc_read_resources(struct device *dev)
 static void soc_init(struct device *dev)
 {
 	mtk_mmu_disable_l2c_sram();
+	mtk_md_early_init();
 }
 
 static struct device_operations soc_ops = {