cpu/x86/mtrr: Use single code path with/without holes
Now that calc_var_mtrrs_with_hole() always chooses the optimal allocation, there is no need for calc_var_mtrrs_without_hole() any more. Drop it and all the logic to decide which one to call. Tests performed compared to "upstream" (before "cpu/x86/mtrr: Optimize hole carving strategy") on a Lenovo/X200s with 48MiB GFX stolen memory. 2GiB total RAM: 3 MTRRs saved MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007ac00000 size 0x7ab40000 type 6 0x000000007ac00000 - 0x00000000d0000000 size 0x55400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 upstream: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/8 > 6. MTRR: default type WB/UC MTRR counts: 4/7. MTRR: WB selected as default type. MTRR: 0 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007b000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 patched: MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007b000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007c000000 mask 0x0000000ffc000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 4GiB total RAM: no MTRRs saved but slightly more accurate alignment MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6 0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017c000000 size 0x7c000000 type 6 upstream: MTRR: default type WB/UC MTRR counts: 7/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000000f00000000 type 6 patched: MTRR: default type WB/UC MTRR counts: 7/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000000f80000000 type 6 8GiB total RAM: possible savings but WB still beats UC MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6 0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000027c000000 size 0x17c000000 type 6 upstream: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/11 > 6. MTRR: default type WB/UC MTRR counts: 4/10. MTRR: WB selected as default type. MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 patched: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/7 > 6. MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 Change-Id: Iedf7dfad61d6baac91973062e2688ad866f05afd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nico Huber
Aaron Durbin
parent
bd5fb66d96
commit
64f0bcb6b0
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@ -133,20 +133,8 @@ static void enable_var_mtrr(unsigned char deftype)
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#define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20)
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#define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32)))
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/*
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* The default MTRR type selection uses 3 approaches for selecting the
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* optimal number of variable MTRRs. For each range do 3 calculations:
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* 1. UC as default type with no holes at top of range.
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* 2. UC as default using holes at top of range.
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* 3. WB as default.
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* If using holes is optimal for a range when UC is the default type the
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* tag is updated to direct the commit routine to use a hole at the top
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* of a range.
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*/
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#define MTRR_ALGO_SHIFT (8)
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#define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1)
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/* If the default type is UC use the hole carving algorithm for a range. */
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#define MTRR_RANGE_UC_USE_HOLE (1 << MTRR_ALGO_SHIFT)
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static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r)
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{
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@ -557,9 +545,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
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struct range_entry *r)
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{
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uint32_t a1, a2, b1, b2;
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uint64_t b2_limit;
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int mtrr_type, carve_hole;
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struct range_entry *next;
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/*
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* Determine MTRRs based on the following algorithm for the given entry:
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@ -597,42 +583,50 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
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a2 = RANGE_4GB;
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b1 = a2;
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b2 = a2;
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carve_hole = 0;
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/*
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* Depending on the type of the next range, there are three
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* different situations to handle:
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*
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* 1. WB range is last in address space:
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* Aligning up, up to the next power of 2, may gain us
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* something.
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*
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* 2. The next range is of type UC:
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* We may align up, up to the _end_ of the next range. If
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* there is a gap between the current and the next range,
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* it would have been covered by the default type UC anyway.
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*
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* 3. The next range is not of type UC:
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* We may align up, up to the _base_ of the next range. This
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* may either be the end of the current range (if the next
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* range follows immediately) or the end of the gap between
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* the ranges.
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*/
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next = memranges_next_entry(var_state->addr_space, r);
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if (next == NULL) {
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b2_limit = ALIGN_UP((uint64_t)b1, 1 << fms(b1));
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/* If it's the last range above 4GiB, we won't carve
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the hole out. If an OS wanted to move MMIO there,
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it would have to override the MTRR setting using
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PAT just like it would with WB as default type. */
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carve_hole = a1 < RANGE_4GB;
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} else if (range_entry_mtrr_type(next) == MTRR_TYPE_UNCACHEABLE) {
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b2_limit = range_entry_end_mtrr_addr(next);
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carve_hole = 1;
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} else {
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b2_limit = range_entry_base_mtrr_addr(next);
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carve_hole = 1;
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/* We only consider WB type ranges for hole-carving. */
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if (mtrr_type == MTRR_TYPE_WRBACK) {
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struct range_entry *next;
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uint64_t b2_limit;
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/*
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* Depending on the type of the next range, there are three
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* different situations to handle:
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*
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* 1. WB range is last in address space:
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* Aligning up, up to the next power of 2, may gain us
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* something.
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*
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* 2. The next range is of type UC:
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* We may align up, up to the _end_ of the next range. If
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* there is a gap between the current and the next range,
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* it would have been covered by the default type UC anyway.
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*
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* 3. The next range is not of type UC:
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* We may align up, up to the _base_ of the next range. This
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* may either be the end of the current range (if the next
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* range follows immediately) or the end of the gap between
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* the ranges.
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*/
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next = memranges_next_entry(var_state->addr_space, r);
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if (next == NULL) {
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b2_limit = ALIGN_UP((uint64_t)b1, 1 << fms(b1));
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/* If it's the last range above 4GiB, we won't carve
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the hole out. If an OS wanted to move MMIO there,
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it would have to override the MTRR setting using
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PAT just like it would with WB as default type. */
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carve_hole = a1 < RANGE_4GB;
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} else if (range_entry_mtrr_type(next)
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== MTRR_TYPE_UNCACHEABLE) {
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b2_limit = range_entry_end_mtrr_addr(next);
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carve_hole = 1;
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} else {
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b2_limit = range_entry_base_mtrr_addr(next);
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carve_hole = 1;
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}
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b2 = optimize_var_mtrr_hole(a1, b1, b2_limit, carve_hole);
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}
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b2 = optimize_var_mtrr_hole(a1, b1, b2_limit, carve_hole);
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calc_var_mtrr_range(var_state, a1, b2 - a1, mtrr_type);
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if (carve_hole && b2 != b1) {
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@ -641,37 +635,6 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
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}
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}
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static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state,
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struct range_entry *r)
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{
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const int mtrr_type = range_entry_mtrr_type(r);
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uint32_t base = range_entry_base_mtrr_addr(r);
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uint32_t end = range_entry_end_mtrr_addr(r);
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/* The end address is within the first 1MiB. The fixed MTRRs take
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* precedence over the variable ones. Therefore this range
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* can be ignored. */
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if (end <= RANGE_1MB)
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return;
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/* Again, the fixed MTRRs take precedence so the beginning
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* of the range can be set to 0 if it starts at or below 1MiB. */
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if (base <= RANGE_1MB)
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base = 0;
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/* If the range starts above 4GiB the processing is done. */
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if (!var_state->above4gb && base >= RANGE_4GB)
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return;
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/* Clip the upper address to 4GiB if addresses above 4GiB
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* are not being processed. */
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if (!var_state->above4gb && end > RANGE_4GB)
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end = RANGE_4GB;
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calc_var_mtrr_range(var_state, base, end - base, mtrr_type);
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}
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static void __calc_var_mtrrs(struct memranges *addr_space,
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int above4gb, int address_bits,
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int *num_def_wb_mtrrs, int *num_def_uc_mtrrs)
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@ -693,16 +656,14 @@ static void __calc_var_mtrrs(struct memranges *addr_space,
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uc_deftype_count = 0;
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/*
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* For each range do 3 calculations:
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* 1. UC as default type with no holes at top of range.
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* 2. UC as default using holes at top of range.
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* 3. WB as default.
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* For each range do 2 calculations:
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* 1. UC as default type with possible holes at top of range.
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* 2. WB as default.
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* The lowest count is then used as default after totaling all
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* MTRRs. Note that the optimal algorithm for UC default is marked in
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* the tag of each range regardless of final decision. UC takes
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* precedence in the MTRR architecture. Therefore, only holes can be
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* used when the type of the region is MTRR_TYPE_WRBACK with
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* MTRR_TYPE_UNCACHEABLE as the default type.
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* MTRRs. UC takes precedence in the MTRR architecture. There-
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* fore, only holes can be used when the type of the region is
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* MTRR_TYPE_WRBACK with MTRR_TYPE_UNCACHEABLE as the default
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* type.
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*/
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memranges_each_entry(r, var_state.addr_space) {
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int mtrr_type;
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@ -710,43 +671,16 @@ static void __calc_var_mtrrs(struct memranges *addr_space,
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mtrr_type = range_entry_mtrr_type(r);
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if (mtrr_type != MTRR_TYPE_UNCACHEABLE) {
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int uc_hole_count;
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int uc_no_hole_count;
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var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE;
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var_state.mtrr_index = 0;
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/* No hole calculation. */
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calc_var_mtrrs_without_hole(&var_state, r);
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uc_no_hole_count = var_state.mtrr_index;
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/* Hole calculation only if type is WB. The 64 number
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* is a count that is unachievable, thus making it
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* a default large number in the case of not doing
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* the hole calculation. */
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uc_hole_count = 64;
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if (mtrr_type == MTRR_TYPE_WRBACK) {
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var_state.mtrr_index = 0;
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calc_var_mtrrs_with_hole(&var_state, r);
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uc_hole_count = var_state.mtrr_index;
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}
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/* Mark the entry with the optimal algorithm. */
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if (uc_no_hole_count < uc_hole_count) {
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uc_deftype_count += uc_no_hole_count;
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} else {
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unsigned long new_tag;
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new_tag = mtrr_type | MTRR_RANGE_UC_USE_HOLE;
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range_entry_update_tag(r, new_tag);
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uc_deftype_count += uc_hole_count;
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}
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var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE;
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calc_var_mtrrs_with_hole(&var_state, r);
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uc_deftype_count += var_state.mtrr_index;
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}
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if (mtrr_type != MTRR_TYPE_WRBACK) {
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var_state.mtrr_index = 0;
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var_state.def_mtrr_type = MTRR_TYPE_WRBACK;
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calc_var_mtrrs_without_hole(&var_state, r);
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calc_var_mtrrs_with_hole(&var_state, r);
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wb_deftype_count += var_state.mtrr_index;
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}
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}
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@ -803,12 +737,7 @@ static void prepare_var_mtrrs(struct memranges *addr_space, int def_type,
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memranges_each_entry(r, var_state.addr_space) {
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if (range_entry_mtrr_type(r) == def_type)
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continue;
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if (def_type == MTRR_TYPE_UNCACHEABLE &&
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(range_entry_tag(r) & MTRR_RANGE_UC_USE_HOLE))
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calc_var_mtrrs_with_hole(&var_state, r);
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else
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calc_var_mtrrs_without_hole(&var_state, r);
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calc_var_mtrrs_with_hole(&var_state, r);
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}
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/* Update the solution. */
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@ -919,9 +848,6 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
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memranges_each_entry(r, orig) {
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unsigned long tag = range_entry_tag(r);
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/* Remove any special tags from original solution. */
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tag &= ~MTRR_RANGE_UC_USE_HOLE;
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/* Remove any write combining MTRRs from the temporary
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* solution as it just fragments the address space. */
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if (tag == MTRR_TYPE_WRCOMB)
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