src/northbridge: Fix typo

Change-Id: I00094028036f33892362b935899e1bceef1da625
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2018-08-07 12:16:56 +02:00 committed by Martin Roth
parent bc0ec507f2
commit 64f6b71af5
10 changed files with 14 additions and 14 deletions

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@ -314,7 +314,7 @@ struct MCTStatStruc;
// for 0x98 index and 0x9c data for DCT0
// for 0x198 index and 0x19c data for DCT1
// even at ganged mode, 0x198/0x19c will be used for channnel B
// even at ganged mode, 0x198/0x19c will be used for channel B
#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
#define DCAO_DctOffset_SHIFT 0
@ -368,9 +368,9 @@ struct MCTStatStruc;
#define DODCC_ProcOdt_75_OHMS 2
/*
for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs
for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0
F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1
for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs
for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0
F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1
So Socket F with Four Logical DIMM will only support DDR2 800 ?
*/
/* there are index +100 ===> for DIMM1

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@ -121,7 +121,7 @@ static void setup_default_resource_map(void)
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit
* This field defines the upp address bits of a 40-bit
* address that defines the end of a memory-mapped
* I/O region n
*/

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@ -157,7 +157,7 @@ typedef struct {
*/
sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
/* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */
/* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */
u8 sysDegree[MAX_NODES];
/* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */
BOOL sysMatrix[MAX_NODES][MAX_NODES];
@ -169,7 +169,7 @@ typedef struct {
u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */
u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */
/* Data for non-coherent initilization */
/* Data for non-coherent initialization */
u8 AutoBusCurrent;
u8 UsedCfgMapEntires;

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@ -1116,7 +1116,7 @@ static u8 readSbLink(cNorthBridge *nb)
* @param[in] *nb = this northbridge
* @return = true - The link has the following status
* LinkCon = 1, Link is connected
* InitComplete = 1,Link initilization is complete
* InitComplete = 1,Link initialization is complete
* NC = 1, Link is coherent
* UniP-cLDT = 0, Link is not Uniprocessor cLDT
* LinkConPend = 0 Link connection is not pending

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@ -846,7 +846,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
dword &= (0x1 << 7);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword);
/* Restore DRAM Adddress/Timing Control Register */
/* Restore DRAM Address/Timing Control Register */
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04);
} else {
/* Disable PHY auto-compensation engine */

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@ -169,7 +169,7 @@ u16 mctGet_NVbits(u8 index)
break;
case NV_SPDCHK_RESTRT:
val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */
//val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
//val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */
//val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */
if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS)

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@ -107,7 +107,7 @@ uintptr_t smm_region_start(void)
}
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)

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@ -59,7 +59,7 @@ static uintptr_t smm_region_start(void)
}
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)

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@ -95,7 +95,7 @@ u32 decode_igd_gtt_size(const u32 gsm)
}
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)

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@ -93,7 +93,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
}
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB aligment. As this may cause very greedy MTRR setup, push
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)