src/northbridge: Fix typo
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -314,7 +314,7 @@ struct MCTStatStruc;
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// for 0x98 index and 0x9c data for DCT0
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// for 0x198 index and 0x19c data for DCT1
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// even at ganged mode, 0x198/0x19c will be used for channnel B
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// even at ganged mode, 0x198/0x19c will be used for channel B
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#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
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#define DCAO_DctOffset_SHIFT 0
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@ -368,9 +368,9 @@ struct MCTStatStruc;
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#define DODCC_ProcOdt_75_OHMS 2
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/*
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for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs
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for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0
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F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1
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for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs
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for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0
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F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1
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So Socket F with Four Logical DIMM will only support DDR2 800 ?
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*/
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/* there are index +100 ===> for DIMM1
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@ -121,7 +121,7 @@ static void setup_default_resource_map(void)
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* 0 = CPU writes may be posted
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* 1 = CPU writes must be non-posted
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* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
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* This field defines the upp adddress bits of a 40-bit
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* This field defines the upp address bits of a 40-bit
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* address that defines the end of a memory-mapped
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* I/O region n
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*/
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@ -157,7 +157,7 @@ typedef struct {
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*/
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sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
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/* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */
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/* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */
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u8 sysDegree[MAX_NODES];
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/* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */
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BOOL sysMatrix[MAX_NODES][MAX_NODES];
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@ -169,7 +169,7 @@ typedef struct {
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u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */
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u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */
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/* Data for non-coherent initilization */
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/* Data for non-coherent initialization */
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u8 AutoBusCurrent;
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u8 UsedCfgMapEntires;
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@ -1116,7 +1116,7 @@ static u8 readSbLink(cNorthBridge *nb)
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* @param[in] *nb = this northbridge
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* @return = true - The link has the following status
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* LinkCon = 1, Link is connected
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* InitComplete = 1,Link initilization is complete
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* InitComplete = 1,Link initialization is complete
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* NC = 1, Link is coherent
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* UniP-cLDT = 0, Link is not Uniprocessor cLDT
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* LinkConPend = 0 Link connection is not pending
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@ -846,7 +846,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
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dword &= (0x1 << 7);
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write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword);
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/* Restore DRAM Adddress/Timing Control Register */
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/* Restore DRAM Address/Timing Control Register */
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write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04);
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} else {
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/* Disable PHY auto-compensation engine */
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@ -169,7 +169,7 @@ u16 mctGet_NVbits(u8 index)
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break;
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case NV_SPDCHK_RESTRT:
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val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */
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//val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */
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//val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */
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//val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */
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if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS)
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@ -107,7 +107,7 @@ uintptr_t smm_region_start(void)
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}
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB aligment. As this may cause very greedy MTRR setup, push
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top(void)
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@ -59,7 +59,7 @@ static uintptr_t smm_region_start(void)
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}
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB aligment. As this may cause very greedy MTRR setup, push
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top(void)
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@ -95,7 +95,7 @@ u32 decode_igd_gtt_size(const u32 gsm)
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}
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB aligment. As this may cause very greedy MTRR setup, push
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top(void)
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@ -93,7 +93,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
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}
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB aligment. As this may cause very greedy MTRR setup, push
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top(void)
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