Further trimming freebios2 towards code reuse.

Unified AMD K8 reset function that can be customized via mainboard Config.lb


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/config/Options.lb

@@ -675,6 +675,21 @@ define HAVE_HARD_RESET
 	export used
 	comment "Have hard reset"
 end
+define HARD_RESET_BUS
+	default 1
+	export always
+	comment "Bus number of southbridge device doing reset"
+end
+define HARD_RESET_DEVICE
+	default 5
+	export always
+	comment "Device number of southbridge device doing reset"
+end
+define HARD_RESET_FUNCTION
+	default 0
+	export always
+	comment "Function number of southbridge device doing reset"
+end
 define MEMORY_HOLE
 	default none
 	export used

src/mainboard/Iwill/DK8S2/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -41,6 +44,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -149,7 +156,6 @@ driver mainboard.o
 #object static_devices.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/Iwill/DK8X/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -41,6 +44,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -149,7 +156,6 @@ driver mainboard.o
 #object static_devices.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/amd/quartet/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -47,6 +50,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -160,7 +167,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/amd/solo/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -47,6 +50,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=5
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -85,8 +92,8 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-#default MAINBOARD_PART_NUMBER="SOLO7"
-#default MAINBOARD_VENDOR="AMD"
+default MAINBOARD_PART_NUMBER="SOLO"
+default MAINBOARD_VENDOR="AMD"
 
 ###
 ### LinuxBIOS layout values
@@ -159,7 +166,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/arima/hdama/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -47,6 +50,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -160,7 +167,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/ibm/e325/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -47,6 +50,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -160,7 +167,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/newisys/khepri/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -47,6 +50,10 @@ default HAVE_FALLBACK_BOOT=1
 ##
 default HAVE_HARD_RESET=1
 
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+
 ##
 ## Build code to export a programmable irq routing table
 ##
@@ -161,7 +168,6 @@ driver mainboard.o
 driver blade3d.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/tyan/s2850/Config.lb

@@ -3,6 +3,9 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses MAINBOARD
 uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 #
 #
 ###
@@ -24,11 +27,15 @@ driver adaptec_scsi.o
 driver promise_sata.o
 driver intel_nic.o
 driver broadcom_nic.o
-object reset.o
+#object reset.o
 #object static_devices.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=2
+default HARD_RESET_FUNCTION=0
+#
 arch i386 end
 #cpu k8 end
 #

src/mainboard/tyan/s2880/Config.lb

@@ -6,6 +6,9 @@ uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 #
 #
 ###
@@ -33,10 +36,14 @@ driver mainboard.o
 #driver adaptec_scsi.o
 #driver promise_sata.o
 #driver intel_nic.o
-object reset.o
+#object reset.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+#
 arch i386 end
 #
 ###

src/mainboard/tyan/s2881/Config.lb

@@ -6,6 +6,9 @@ uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 #
 #
 ###
@@ -35,10 +38,14 @@ driver mainboard.o
 #driver si_sata.o
 #driver intel_nic.o
 #driver broadcom_nic.o
-object reset.o
+#object reset.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+#
 arch i386 end
 #cpu k8 end
 #

src/mainboard/tyan/s2882/Config.lb

@@ -6,6 +6,9 @@ uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 #
 #
 ###
@@ -34,10 +37,14 @@ driver mainboard.o
 #driver si_sata.o
 driver intel_nic.o
 #driver broadcom_nic.o
-object reset.o
+#object reset.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+#
 arch i386 end
 #cpu k8 end
 #

src/mainboard/tyan/s2885/Config.lb

@@ -6,6 +6,9 @@ uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 
 #
 #
@@ -37,10 +40,14 @@ driver mainboard.o
 #driver adaptec_scsi.o
 #driver si_sata.o
 #driver intel_nic.o
-object reset.o
+#object reset.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-
+#
+default HARD_RESET_BUS=3
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+#
 #
 arch i386 end
 

src/mainboard/tyan/s4880/Config.lb

@@ -6,6 +6,9 @@ uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
 #
 #
 ###
@@ -34,10 +37,14 @@ driver mainboard.o
 #driver adaptec_scsi.o
 #driver si_sata.o
 #driver intel_nic.o
-object reset.o
+#object reset.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+#
 arch i386 end
 #cpu k8 end
 #

src/southbridge/amd/amd8111/Config.lb

@@ -8,3 +8,4 @@ driver amd8111_usb2.o
 driver amd8111_ac97.o
 driver amd8111_nic.o
 driver amd8111_pci.o
+object amd8111_reset.o

src/southbridge/amd/amd8111/amd8111_reset.c

@@ -0,0 +1,45 @@
+#include <arch/io.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+#define AMD8111_RESET PCI_DEV(     \
+		HARD_RESET_BUS,    \
+		HARD_RESET_DEVICE, \
+		HARD_RESET_FUNCTION)
+
+typedef unsigned device_t;
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+        unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+        addr = dev | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	pci_write_config8(AMD8111_RESET, 0x47, 1);
+}