- remove old cpu header files
- Update cpu.h for the new cpu initialization scheme git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
c84c1906b7
commit
65186ce66c
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@ -1,16 +1,16 @@
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#ifndef CPU_CPU_H
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#define CPU_CPU_H
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#include <mem.h>
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struct device;
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#include <arch/cpu.h>
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unsigned long cpu_initialize(struct mem_range *mem);
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#define CPU_ENABLED 1 /* Processor is available */
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#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
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void cpu_initialize(void);
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void initialize_cpus(struct device *root);
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#define __cpu_driver __attribute__ ((unused,__section__(".rodata.cpu_driver")))
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#define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
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/** start of compile time generated pci driver array */
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extern struct pci_driver cpu_drivers[];
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extern struct cpu_driver cpu_drivers[];
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/** end of compile time generated pci driver array */
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extern struct pci_driver ecpu_drivers[];
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extern struct cpu_driver ecpu_drivers[];
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#endif /* CPU_CPU_H */
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@ -1,29 +0,0 @@
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#ifndef CPU_CPUFIXUP_H
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#define CPU_CPUFIXUP_H
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struct mem_range;
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#include <cpu/k8/cpufixup.h>
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#include <cpu/k7/cpufixup.h>
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#include <cpu/p6/cpufixup.h>
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#if CPU_FIXUP == 1
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# if (k8==1)
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#warning "====>Temporary notice that we are using k8 cpufixup"
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# define cpufixup(mem) k8_cpufixup(mem)
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# elif (k7==1)
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#warning "====>Temporary notice that we are using k7 cpufixup"
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# define cpufixup(mem) k7_cpufixup(mem)
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# elif (i786==1)
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#warning "====>Temporary notice that we are using i786 cpufixup"
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# define cpufixup(mem) i786_cpufixup(mem)
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# elif (i686==1)
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#warning "====>Temporary notice that we are using i686 cpufixup"
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# define cpufixup(mem) p6_cpufixup(mem)
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# endif
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#else
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#warning "====>YOU DID NOT DEFINE ONE OF: k8, k7, i786, i686"
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# define cpufixup(mem) do {} while(0)
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#endif
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#endif /* CPU_CPUFIXUP_H */
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@ -1,6 +0,0 @@
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#ifndef CPU_K7_CPUFIXUP_H
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#define CPU_K7_CPUFIXUP_H
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void k7_cpufixup(struct mem_range *mem);
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#endif /* CPU_K7_CPUFIXUP_H */
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@ -1,42 +0,0 @@
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#ifndef CPU_K7_MTRR_H
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#define CPU_K7_MTRR_H
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#include <cpu/p6/mtrr.h>
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#define IORR_FIRST 0xC0010016
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#define IORR_LAST 0xC0010019
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#define SYSCFG 0xC0010010
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#define MTRR_READ_MEM (1 << 4)
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#define MTRR_WRITE_MEM (1 << 3)
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#define SYSCFG_MSR 0xC0010010
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#define SYSCFG_MSR_EvictEn (1 << 22)
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#define SYSCFG_MSR_TOM2En (1 << 21)
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#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
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#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
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#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
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#define SYSCFG_MSR_UcLockEn (1 << 17)
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#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
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#define SYSCFG_MSR_SysEccEn (1 << 15)
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#define SYSCFG_MSR_RdBlkL2WayEn (1 << 14)
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#define SYSCFG_MSR_SysFillValIsD1 (1 << 13)
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#define SYSCFG_MSR_IcInclusive (1 << 12)
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#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
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#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
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#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
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#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
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#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
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#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
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#define IORR0_BASE 0xC0010016
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#define IORR0_MASK 0xC0010017
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#define IORR1_BASE 0xC0010018
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#define IORR1_MASK 0xC0010019
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#define TOP_MEM 0xC001001A
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#define TOP_MEM2 0xC001001D
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#define HWCR_MSR 0xC0010015
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#endif /* CPU_K7_MTRR_H */
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@ -1,6 +0,0 @@
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#ifndef CPU_K8_CPUFIXUP_H
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#define CPU_K8_CPUFIXUP_H
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void k8_cpufixup(struct mem_range *mem);
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#endif /* CPU_K8_CPUFIXUP_H */
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@ -1,41 +0,0 @@
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#ifndef CPU_K8_MTRR_H
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#define CPU_K8_MTRR_H
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#include <cpu/p6/mtrr.h>
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#define IORR_FIRST 0xC0010016
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#define IORR_LAST 0xC0010019
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#define MTRR_READ_MEM (1 << 4)
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#define MTRR_WRITE_MEM (1 << 3)
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#define SYSCFG_MSR 0xC0010010
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#define SYSCFG_MSR_TOM2En (1 << 21)
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#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
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#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
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#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
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#define SYSCFG_MSR_UcLockEn (1 << 17)
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#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
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#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
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#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
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#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
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#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
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#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
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#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
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#define IORR0_BASE 0xC0010016
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#define IORR0_MASK 0xC0010017
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#define IORR1_BASE 0xC0010018
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#define IORR1_MASK 0xC0010019
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#define TOP_MEM 0xC001001A
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#define TOP_MEM2 0xC001001D
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#define HWCR_MSR 0xC0010015
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#define NB_CFG_MSR 0xC001001f
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#define IC_CFG_MSR 0xC0011021
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#define DC_CFG_MSR 0xC0011022
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#define BU_CFG_MSR 0xC0011023
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#define TOP_MEM_MASK 0x007fffff
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#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
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#endif /* CPU_K8_MTRR_H */
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@ -1,25 +0,0 @@
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#ifndef CPU_P5_CPUID_H
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#define CPU_P5_CPUID_H
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int mtrr_check(void);
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void display_cpuid(void);
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/*
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* Generic CPUID function. copied from Linux kernel headers
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*/
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static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
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{
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__asm__("pushl %%ebx\n\t"
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"cpuid\n\t"
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"movl %%ebx, %%esi\n\t"
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"popl %%ebx\n\t"
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: "=a" (*eax),
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"=S" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "a" (op)
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: "cc");
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}
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#endif /* CPU_P5_CPUID_H */
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@ -1,191 +0,0 @@
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#ifndef APIC_H
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#define APIC_H
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#define APIC_BASE_MSR 0x1B
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#define APIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
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#define APIC_BASE_MSR_ENABLE (1 << 11)
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#define APIC_BASE_MSR_ADDR_MASK 0xFFFFF000
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#define APIC_DEFAULT_BASE 0xfee00000
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#define APIC_ID 0x020
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#define APIC_LVR 0x030
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#define APIC_TASKPRI 0x80
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#define APIC_TPRI_MASK 0xFF
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#define APIC_ARBID 0x090
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#define APIC_RRR 0x0C0
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#define APIC_SVR 0x0f0
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#define APIC_SPIV 0x0f0
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#define APIC_SPIV_ENABLE 0x100
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#define APIC_ESR 0x280
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#define APIC_ESR_SEND_CS 0x00001
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#define APIC_ESR_RECV_CS 0x00002
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#define APIC_ESR_SEND_ACC 0x00004
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#define APIC_ESR_RECV_ACC 0x00008
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#define APIC_ESR_SENDILL 0x00020
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#define APIC_ESR_RECVILL 0x00040
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#define APIC_ESR_ILLREGA 0x00080
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#define APIC_ICR 0x300
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#define APIC_DEST_SELF 0x40000
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#define APIC_DEST_ALLINC 0x80000
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#define APIC_DEST_ALLBUT 0xC0000
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#define APIC_ICR_RR_MASK 0x30000
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#define APIC_ICR_RR_INVALID 0x00000
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#define APIC_ICR_RR_INPROG 0x10000
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#define APIC_ICR_RR_VALID 0x20000
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#define APIC_INT_LEVELTRIG 0x08000
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#define APIC_INT_ASSERT 0x04000
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#define APIC_ICR_BUSY 0x01000
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#define APIC_DEST_LOGICAL 0x00800
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#define APIC_DM_FIXED 0x00000
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#define APIC_DM_LOWEST 0x00100
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#define APIC_DM_SMI 0x00200
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#define APIC_DM_REMRD 0x00300
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#define APIC_DM_NMI 0x00400
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#define APIC_DM_INIT 0x00500
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#define APIC_DM_STARTUP 0x00600
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#define APIC_DM_EXTINT 0x00700
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#define APIC_VECTOR_MASK 0x000FF
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#define APIC_ICR2 0x310
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#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
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#define SET_APIC_DEST_FIELD(x) ((x)<<24)
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#define APIC_LVTT 0x320
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#define APIC_LVTPC 0x340
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#define APIC_LVT0 0x350
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#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
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#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
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#define SET_APIC_TIMER_BASE(x) (((x)<<18))
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#define APIC_TIMER_BASE_CLKIN 0x0
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#define APIC_TIMER_BASE_TMBASE 0x1
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#define APIC_TIMER_BASE_DIV 0x2
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#define APIC_LVT_TIMER_PERIODIC (1<<17)
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#define APIC_LVT_MASKED (1<<16)
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#define APIC_LVT_LEVEL_TRIGGER (1<<15)
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#define APIC_LVT_REMOTE_IRR (1<<14)
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#define APIC_INPUT_POLARITY (1<<13)
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#define APIC_SEND_PENDING (1<<12)
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#define APIC_LVT_RESERVED_1 (1<<11)
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#define APIC_DELIVERY_MODE_MASK (7<<8)
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#define APIC_DELIVERY_MODE_FIXED (0<<8)
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#define APIC_DELIVERY_MODE_NMI (4<<8)
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#define APIC_DELIVERY_MODE_EXTINT (7<<8)
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#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
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#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
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#define APIC_MODE_FIXED 0x0
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#define APIC_MODE_NMI 0x4
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#define APIC_MODE_EXINT 0x7
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#define APIC_LVT1 0x360
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#define APIC_LVTERR 0x370
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#define APIC_TMICT 0x380
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#define APIC_TMCCT 0x390
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#define APIC_TDCR 0x3E0
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#define APIC_TDR_DIV_TMBASE (1<<2)
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#define APIC_TDR_DIV_1 0xB
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#define APIC_TDR_DIV_2 0x0
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#define APIC_TDR_DIV_4 0x1
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#define APIC_TDR_DIV_8 0x2
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#define APIC_TDR_DIV_16 0x3
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#define APIC_TDR_DIV_32 0x8
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#define APIC_TDR_DIV_64 0x9
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#define APIC_TDR_DIV_128 0xA
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#if defined(__ROMCC__) || !defined(ASSEMBLY)
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static inline unsigned long apic_read(unsigned long reg)
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{
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return *((volatile unsigned long *)(APIC_DEFAULT_BASE+reg));
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}
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static inline void apic_write(unsigned long reg, unsigned long v)
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{
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*((volatile unsigned long *)(APIC_DEFAULT_BASE+reg)) = v;
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}
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static inline void apic_wait_icr_idle(void)
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{
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do { } while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
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}
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#endif
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#if !defined(ASSEMBLY)
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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extern inline void apic_write_atomic(unsigned long reg, unsigned long v)
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{
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xchg((volatile unsigned long *)(APIC_DEFAULT_BASE+reg), v);
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}
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x,y) apic_write((x),(y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x,y) apic_write_atomic((x),(y))
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#endif
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static inline int apic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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apic_wait_icr_idle();
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write_around(APIC_ICR, APIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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#if 0
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udelay(100);
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#endif
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status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
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} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == APIC_ICR_RR_VALID) {
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*pvalue = apic_read(APIC_RRR);
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result = 0;
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}
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return result;
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}
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#endif /* ASSEMBLY */
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#endif /* APIC_H */
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@ -1,6 +0,0 @@
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#ifndef CPU_P6_CPUFIXUP_H
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#define CPU_P6_CPUFIXUP_H
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void p6_cpufixup(struct mem_range *mem);
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#endif /* CPU_P6_CPUFIXUP_H */
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@ -1,101 +0,0 @@
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#ifndef CPU_P6_MSR_H
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#define CPU_P6_MSR_H
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#ifdef __ROMCC__
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typedef __builtin_msr_t msr_t;
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static msr_t rdmsr(unsigned long index)
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{
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return __builtin_rdmsr(index);
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}
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static void wrmsr(unsigned long index, msr_t msr)
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{
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__builtin_wrmsr(index, msr.lo, msr.hi);
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}
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struct tsc_struct {
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unsigned lo;
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unsigned hi;
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};
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typedef struct tsc_struct tsc_t;
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static tsc_t rdtsc(void)
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{
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tsc_t res;
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asm ("rdtsc"
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: "=a" (res.lo), "=d"(res.hi) /* outputs */
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: /* inputs */
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: /* Clobbers */
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);
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return res;
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}
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#endif
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#ifdef __GNUC__
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typedef struct msr_struct
|
||||
{
|
||||
unsigned lo;
|
||||
unsigned hi;
|
||||
} msr_t;
|
||||
|
||||
static inline msr_t rdmsr(unsigned index)
|
||||
{
|
||||
msr_t result;
|
||||
__asm__ __volatile__ (
|
||||
"rdmsr"
|
||||
: "=a" (result.lo), "=d" (result.hi)
|
||||
: "c" (index)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline void wrmsr(unsigned index, msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
: /* No outputs */
|
||||
: "c" (index), "a" (msr.lo), "d" (msr.hi)
|
||||
);
|
||||
}
|
||||
|
||||
typedef struct tsc_struct
|
||||
{
|
||||
unsigned lo;
|
||||
unsigned hi;
|
||||
} tsc_t;
|
||||
|
||||
static inline tsc_t rdtsc(void)
|
||||
{
|
||||
tsc_t result;
|
||||
__asm__ __volatile__(
|
||||
"rdtsc"
|
||||
: "=a" (result.lo), "=d" (result.hi)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
typedef struct pmc_struct
|
||||
{
|
||||
unsigned lo;
|
||||
unsigned hi;
|
||||
} pmc_t;
|
||||
|
||||
static inline pmc_t rdpmc(unsigned counter)
|
||||
{
|
||||
pmc_t result;
|
||||
__asm__ __volatile__(
|
||||
"rdpmc"
|
||||
: "=a" (result.lo), "=d" (result.hi)
|
||||
: "c" (counter)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CPU_P6_MSR_H */
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
#ifndef __LINUXBIOS_CPU_P6_MTRR_H
|
||||
#define __LINUXBIOS_CPU_P6_MTRR_H
|
||||
|
||||
/* These are the region types */
|
||||
#define MTRR_TYPE_UNCACHEABLE 0
|
||||
#define MTRR_TYPE_WRCOMB 1
|
||||
/*#define MTRR_TYPE_ 2*/
|
||||
/*#define MTRR_TYPE_ 3*/
|
||||
#define MTRR_TYPE_WRTHROUGH 4
|
||||
#define MTRR_TYPE_WRPROT 5
|
||||
#define MTRR_TYPE_WRBACK 6
|
||||
#define MTRR_NUM_TYPES 7
|
||||
|
||||
#define MTRRcap_MSR 0x0fe
|
||||
#define MTRRdefType_MSR 0x2ff
|
||||
|
||||
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
|
||||
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
||||
|
||||
#define NUM_FIXED_RANGES 88
|
||||
#define MTRRfix64K_00000_MSR 0x250
|
||||
#define MTRRfix16K_80000_MSR 0x258
|
||||
#define MTRRfix16K_A0000_MSR 0x259
|
||||
#define MTRRfix4K_C0000_MSR 0x268
|
||||
#define MTRRfix4K_C8000_MSR 0x269
|
||||
#define MTRRfix4K_D0000_MSR 0x26a
|
||||
#define MTRRfix4K_D8000_MSR 0x26b
|
||||
#define MTRRfix4K_E0000_MSR 0x26c
|
||||
#define MTRRfix4K_E8000_MSR 0x26d
|
||||
#define MTRRfix4K_F0000_MSR 0x26e
|
||||
#define MTRRfix4K_F8000_MSR 0x26f
|
||||
|
||||
|
||||
#if !defined(ASSEMBLY)
|
||||
|
||||
void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type);
|
||||
void add_var_mtrr(unsigned long basek, unsigned long sizek, unsigned char type);
|
||||
#if defined(INTEL_PPRO_MTRR)
|
||||
struct mem_range;
|
||||
void setup_mtrrs(struct mem_range *mem);
|
||||
#endif
|
||||
|
||||
#endif /* ASSEMBLY */
|
||||
|
||||
#endif /* __LINUXBIOS_CPU_P6_MTRR_H */
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef CPU_P6_PGTBL_H
|
||||
#define CPU_P6_PGTBL_H
|
||||
|
||||
#define MAPPING_ERROR ((void *)0xffffffffUL)
|
||||
void *map_2M_page(int cpu_index, unsigned long page);
|
||||
|
||||
#endif /* CPU_P6_PGTBL_H */
|
||||
Loading…
Reference in New Issue