diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index fc970baee1..60e7a749ba 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -24,7 +24,7 @@ void intel_sandybridge_finalize_smm(void)
 	pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0);
 	pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2);
 	pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0);
-	pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10);
+	pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10);
 	pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0);
 	pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0);
 	pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index b12ea25f25..0ba1678807 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -585,33 +585,33 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
 	pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg);
 
 	if (me_uma_size) {
-		reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4);
+		reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4);
 		val = (0x80000 - me_uma_size) & 0xfffff000;
 		reg = (reg & ~0x000fffff) | (val >> 12);
-		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg);
-		pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg);
+		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg);
+		pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg);
 
 		// ME base
-		reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE);
+		reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE);
 		val = mestolenbase & 0xfff;
 		reg = (reg & ~0xfff00000) | (val << 20);
-		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg);
-		pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg);
+		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg);
+		pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg);
 
-		reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4);
+		reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4);
 		val = mestolenbase & 0xfffff000;
 		reg = (reg & ~0x000fffff) | (val >> 12);
-		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg);
-		pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg);
+		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg);
+		pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg);
 
 		// ME mask
-		reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK);
+		reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK);
 		val = (0x80000 - me_uma_size) & 0xfff;
 		reg = (reg & ~0xfff00000) | (val << 20);
 		reg = reg | (1 << 10);	// set lockbit on ME mem
 		reg = reg | (1 << 11);	// set ME memory enable
-		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg);
-		pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg);
+		printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg);
+		pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg);
 	}
 }
 
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 6bfe88b814..6a9c00f396 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -82,8 +82,8 @@ enum platform_type {
 #define PAVPC		0x58	/* Protected Audio Video Path Control */
 #define DPR		0x5c	/* DMA Protected Range */
 
-#define MEBASE		0x70
-#define MEMASK		0x78
+#define MESEG_BASE	0x70
+#define MESEG_MASK	0x78
 
 #define PAM0		0x80
 #define PAM1		0x81