soc/intel/apollolake: Perform CPU MP Init before FSP-S Init
As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=none BRANCH=none TEST=Build and boot Reef Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20037 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -147,7 +147,7 @@ static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = apollolake_init_cpus,
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.init = DEVICE_NOOP,
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.scan_bus = NULL,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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};
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@ -16,6 +16,8 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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@ -25,8 +27,10 @@
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#include <cpu/x86/mtrr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <intelblocks/fast_spi.h>
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#include <reg_script.h>
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#include <romstage_handoff.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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@ -108,16 +112,19 @@ static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
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}
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/*
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* Do essential initialization tasks before APs can be fired up
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* Do essential initialization tasks before APs can be fired up -
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*
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* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
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* creates the MTRR solution that the APs will use. Otherwise APs will try to
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* apply the incomplete solution as the BSP is calculating it.
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* Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
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* that are set prior to ramstage.
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* Real MTRRs programming are being done after resource allocation.
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*
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* Do, FSP loading before MP Init to ensure that the FSP cmponent stored in
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* external stage cache in TSEG does not flush off due to SMM relocation
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* during MP Init stage.
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*/
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static void pre_mp_init(void)
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{
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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fsps_load(romstage_handoff_is_resume());
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}
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/* Find CPU topology */
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@ -199,14 +206,32 @@ static const struct mp_ops mp_ops = {
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.post_mp_init = southbridge_smm_enable_smi,
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};
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void apollolake_init_cpus(device_t dev)
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static void soc_init_cpus(void *unused)
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{
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device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
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assert(dev != NULL);
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/* Clear for take-off */
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if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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/* Ensure to re-program all MTRRs based on DRAM resource settings */
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static void soc_post_cpus_init(void *unused)
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{
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if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
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printk(BIOS_ERR, "MTRR programming failure\n");
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/* Temporarily cache the memory-mapped boot media. */
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if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
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IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
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fast_spi_cache_bios_region();
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x86_mtrr_check();
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}
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/*
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* Do CPU MP Init before FSP Silicon Init
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*/
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL);
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);
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@ -24,7 +24,6 @@
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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void apollolake_init_cpus(struct device *dev);
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void set_max_freq(void);
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void enable_untrusted_mode(void);
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#endif
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