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nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops 

On desktop boards the PPD bit of MRS register MR0 is set and thus
DLL_Off mode shouldn't be used, as enforced by datasheet
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1.

Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2017-10-31 11:36:55 +01:00 committed by Felix Held
parent 8ba9e8cf63
commit 652c491917
2 changed files with 11 additions and 3 deletions
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9
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -3202,7 +3202,14 @@ void final_registers(ramctr_timing * ctrl)
write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740);
if (ctrl->mobile)
/* APD - DLL Off, 64 DCLKs until idle, decision per rank */
MCHBAR32(PM_PDWN_Config) = 0x00000740;
else
/* APD - PPD, 64 DCLKs until idle, decision per rank */
MCHBAR32(PM_PDWN_Config) = 0x00000340;
write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK
write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK
write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK

5
src/northbridge/intel/sandybridge/raminit_common.h
View File

@ -150,8 +150,9 @@ typedef struct ramctr_timing_st {
#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)
#define GET_ERR_CHANNEL(x) (x>>16)
#define MC_BIOS_REQ 0x5e00
#define MC_BIOS_DATA 0x5e04
#define MC_BIOS_REQ 0x5e00
#define MC_BIOS_DATA 0x5e04
#define PM_PDWN_Config 0x4cb0
u8 get_CWL(u32 tCK);
void dram_mrscommands(ramctr_timing * ctrl);