GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants 

Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2
variants in order to provide the real delay value for the VCC supply
rail. This delay is needed to enable proper switching between different
VCC levels based on current system state.

Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Werner Zeh 2022-10-20 15:49:21 +02:00 committed by Martin L Roth
parent 516eff01e6
commit 6537216b7a
2 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
View File

@ -126,6 +126,12 @@ chip soc/intel/elkhartlake
register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
register "PchTsnGbeSgmiiEnable" = "1"
# FIVR related settings
register "fivr" = "{
.fivr_config_en = true,
.vcc_low_high_us = 50,
}"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device

6
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
View File

@ -117,6 +117,12 @@ chip soc/intel/elkhartlake
},
}"
# FIVR related settings
register "fivr" = "{
.fivr_config_en = true,
.vcc_low_high_us = 50,
}"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device