mb/google/octopus: add support for new shared memory config
Allow for shared dram configuration by introducing a new table that collapses the common settings after removing the part numbers. When employing this scheme the part number comes from CBI. BUG=b:112203105 TEST=Placed part number in cbi. Faked out memory sku id. And enabled DRAM part num always in cbi. Everything checked out. Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -14,6 +14,7 @@
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*/
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <compiler.h>
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#include <gpio.h>
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#include <soc/meminit.h>
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@ -63,7 +64,7 @@ const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
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},
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};
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static const struct lpddr4_sku skus[] = {
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static const struct lpddr4_sku non_cbi_skus[] = {
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/*
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* K4F6E304HB-MGCJ - both logical channels While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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@ -140,15 +141,75 @@ static const struct lpddr4_sku skus[] = {
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},
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};
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static const struct lpddr4_cfg lp4cfg = {
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.skus = skus,
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.num_skus = ARRAY_SIZE(skus),
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static const struct lpddr4_cfg non_cbi_lp4cfg = {
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.skus = non_cbi_skus,
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.num_skus = ARRAY_SIZE(non_cbi_skus),
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.swizzle_config = &baseboard_lpddr4_swizzle,
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};
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static const struct lpddr4_sku cbi_skus[] = {
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/* Dual Channel Config 4GiB System Capacity */
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[0] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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},
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/* Dual Channel Config 8GiB System Capacity */
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[1] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_16Gb_DENSITY,
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.ch1_rank_density = LP4_16Gb_DENSITY,
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},
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/* Dual Channel Config 8GiB System Capacity */
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[2] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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},
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/* Single Channel Configs 4GiB System Capacity Ch0 populated. */
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[3] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_16Gb_DENSITY,
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},
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/* Single Channel Configs 4GiB System Capacity Ch0 populated. */
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[4] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch0_dual_rank = 1,
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},
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/* Single Channel Configs 4GiB System Capacity Ch1 populated. */
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[5] = {
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.speed = LP4_SPEED_2400,
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.ch1_rank_density = LP4_16Gb_DENSITY,
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},
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/* Single Channel Configs 4GiB System Capacity Ch1 populated. */
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[6] = {
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.speed = LP4_SPEED_2400,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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.ch1_dual_rank = 1,
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},
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};
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static const struct lpddr4_cfg cbi_lp4cfg = {
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.skus = cbi_skus,
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.num_skus = ARRAY_SIZE(cbi_skus),
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.swizzle_config = &baseboard_lpddr4_swizzle,
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};
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const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
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{
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return &lp4cfg;
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if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI))
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return &non_cbi_lp4cfg;
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if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
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/* Fall back non cbi memory config. */
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if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
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return &non_cbi_lp4cfg;
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}
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return &cbi_lp4cfg;
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}
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size_t __weak variant_memory_sku(void)
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