nb/intel/pineview: Change signature of `decode_pciebar`

Rename it and make it return an int, like other northbridges do.

Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/pineview/acpi.c

@@ -11,7 +11,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	u32 length, pciexbar;
 
-	if (!decode_pciebar(&pciexbar, &length))
+	if (!decode_pcie_bar(&pciexbar, &length))
 		return current;
 
 	const int max_buses = length / MiB;

src/northbridge/intel/pineview/memmap.c

@@ -15,7 +15,7 @@
 #include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 
-u8 decode_pciebar(u32 *const base, u32 *const len)
+int decode_pcie_bar(u32 *const base, u32 *const len)
 {
 	*base = 0;
 	*len = 0;

src/northbridge/intel/pineview/northbridge.c

@@ -114,7 +114,7 @@ static void mch_domain_read_resources(struct device *dev)
 			(touud - top32memk) >> 10);
 	}
 
-	if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
+	if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
 		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
 			pcie_config_base, pcie_config_size);
 

src/northbridge/intel/pineview/pineview.h

@@ -185,7 +185,7 @@ struct sysinfo {
 void pineview_early_init(void);
 u32 decode_igd_memory_size(const u32 gms);
 u32 decode_igd_gtt_size(const u32 gsm);
-u8 decode_pciebar(u32 *const base, u32 *const len);
+int decode_pcie_bar(u32 *const base, u32 *const len);
 
 /* Mainboard romstage callback functions */
 void get_mb_spd_addrmap(u8 *spd_addr_map);