nb/intel/pineview: Change signature of `decode_pciebar`
Rename it and make it return an int, like other northbridges do. Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -11,7 +11,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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{
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{
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u32 length, pciexbar;
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u32 length, pciexbar;
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if (!decode_pciebar(&pciexbar, &length))
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if (!decode_pcie_bar(&pciexbar, &length))
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return current;
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return current;
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const int max_buses = length / MiB;
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const int max_buses = length / MiB;
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@ -15,7 +15,7 @@
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/intel/smm_reloc.h>
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#include <stdint.h>
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#include <stdint.h>
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u8 decode_pciebar(u32 *const base, u32 *const len)
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int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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{
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*base = 0;
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*base = 0;
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*len = 0;
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*len = 0;
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@ -114,7 +114,7 @@ static void mch_domain_read_resources(struct device *dev)
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(touud - top32memk) >> 10);
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(touud - top32memk) >> 10);
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}
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}
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if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
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if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
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printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
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printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
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pcie_config_base, pcie_config_size);
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pcie_config_base, pcie_config_size);
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@ -185,7 +185,7 @@ struct sysinfo {
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void pineview_early_init(void);
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void pineview_early_init(void);
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u32 decode_igd_memory_size(const u32 gms);
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u32 decode_igd_memory_size(const u32 gms);
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u32 decode_igd_gtt_size(const u32 gsm);
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u32 decode_igd_gtt_size(const u32 gsm);
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u8 decode_pciebar(u32 *const base, u32 *const len);
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int decode_pcie_bar(u32 *const base, u32 *const len);
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/* Mainboard romstage callback functions */
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/* Mainboard romstage callback functions */
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void get_mb_spd_addrmap(u8 *spd_addr_map);
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void get_mb_spd_addrmap(u8 *spd_addr_map);
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