diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 992c957913..6f61fc37fd 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -113,6 +113,11 @@ static void model_10xxx_init(device_t dev)
 	msr.hi &= ~(1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 
+	/* Clear ClLinesToNbDis */
+	msr = rdmsr(BU_CFG2_MSR);
+	msr.lo &= ~(1 << 15);
+	wrmsr(BU_CFG2_MSR, msr);
+
 	/* Write protect SMM space with SMMLOCK. */
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= (1 << 0);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index afeb4e98d2..c571b2349d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3189,7 +3189,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
 	print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n");
 
 
-	mct_ClrClToNB_D(pMCTstat, pDCTstat);
+	/* ClrClToNB_D postponed til we're done executing from ROM */
 	mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
 }