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soc/intel/tigerlake: Match RP number with TGL EDS 

Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.

BUG=b:151208838
TEST=build RVP successfully

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
This commit is contained in:
Wonkyu Kim 2020-03-12 18:35:35 -07:00 committed by Patrick Georgi
parent 4d5fd77cf8
commit 655dba4055
1 changed files with 0 additions and 68 deletions
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68
src/soc/intel/tigerlake/acpi/pcie.asl
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@ -312,71 +312,3 @@ Device (RP12)
Return (IRQM (RPPN))
}
}
Device (RP13)
{
Name (_ADR, 0x001D0004)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP14)
{
Name (_ADR, 0x001D0005)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP15)
{
Name (_ADR, 0x001D0006)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP16)
{
Name (_ADR, 0x001D0007)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}