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soc/amd/stoneyridge: Configure FCH for TPM 

In preparation for moving AGESA calls out of the bootblock:
* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy
TPM IO 0x7f-0x7e and 0xef-0xee
* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.

BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)

Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Garrett Kirkendall 2018-03-07 16:12:11 -06:00 committed by Patrick Georgi
parent be33a674bb
commit 6575306663
2 changed files with 35 additions and 0 deletions
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5
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -186,6 +186,10 @@
#define LPC_MISC_CONTROL_BITS 0x78
#define LPC_NOHOG BIT(0)
#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
#define TPM_12_EN BIT(0)
#define TPM_LEGACY_EN BIT(2)
#define LPC_WIDEIO2_GENERIC_PORT 0x90
/*
@ -357,6 +361,7 @@ void sb_pci_port80(void);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
void sb_set_readspeed(u16 norm, u16 fast);
void sb_tpm_decode(void);
void sb_tpm_decode_spi(void);
void lpc_wideio_512_window(uint16_t base);
void lpc_wideio_16_window(uint16_t base);

30
src/soc/amd/stoneyridge/southbridge.c
View File

@ -470,8 +470,38 @@ void sb_read_mode(u32 mode)
& ~SPI_READ_MODE_MASK) | mode);
}
/*
* Enable FCH to decode TPM associated Memory and IO regions
*
* Enable decoding of TPM cycles defined in TPM 1.2 spec
* Enable decoding of legacy TPM addresses: IO addresses 0x7f-
* 0x7e and 0xef-0xee.
* This function should be called if TPM is connected in any way to the FCH and
* conforms to the regions decoded.
* Absent any other routing configuration the TPM cycles will be claimed by the
* LPC bus
*/
void sb_tpm_decode(void)
{
u32 value;
value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE);
value |= TPM_12_EN | TPM_LEGACY_EN;
pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
}
/*
* Enable FCH to decode TPM associated Memory and IO regions to SPI
*
* This should be used if TPM is connected to SPI bus.
* Assumes SPI address space is already configured via a call to sb_spibase().
*/
void sb_tpm_decode_spi(void)
{
/* Enable TPM decoding to FCH */
sb_tpm_decode();
/* Route TPM accesses to SPI */
u32 spibase = pci_read_config32(SOC_LPC_DEV,
SPIROM_BASE_ADDRESS_REGISTER);
pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase