soc/amd/cezanne: use common TSC and monotonic timer code

Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2020-12-04 17:38:46 +01:00
parent 2f5c759077
commit 65783fbeb4
3 changed files with 1 additions and 10 deletions

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@ -17,8 +17,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select NO_MONOTONIC_TIMER # TODO: replace select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select UNKNOWN_TSC_RATE # TODO: replace
config EARLY_RESERVED_DRAM_BASE config EARLY_RESERVED_DRAM_BASE
hex hex

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@ -7,7 +7,6 @@ bootblock-y += bootblock.c
romstage-y += romstage.c romstage-y += romstage.c
ramstage-y += chip.c ramstage-y += chip.c
ramstage-y += timer.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include

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@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h>
void init_timer(void)
{
}