soc/amd/cezanne: use common TSC and monotonic timer code

Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/Kconfig

@@ -17,8 +17,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
-	select NO_MONOTONIC_TIMER		# TODO: replace
+	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
-	select UNKNOWN_TSC_RATE			# TODO: replace
 
 config EARLY_RESERVED_DRAM_BASE
 	hex

src/soc/amd/cezanne/Makefile.inc

@@ -7,7 +7,6 @@ bootblock-y	+= bootblock.c
 romstage-y	+= romstage.c
 
 ramstage-y	+= chip.c
-ramstage-y	+= timer.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
 

src/soc/amd/cezanne/timer.c

@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <delay.h>
-
-void init_timer(void)
-{
-}