From 658d7c56b8621b1682ce0f2e457e6abce7308851 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 15 Sep 2021 16:03:40 +0800 Subject: [PATCH] mb/google/brya: Correct SSD power sequence SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199822704 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Eric Lai Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/baseboard/brya/gpio.c | 2 ++ src/mainboard/google/brya/variants/brya0/gpio.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index c11cf42254..73fad72480 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -388,6 +388,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index 6ca5e98d53..274ddbeb42 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -74,6 +74,8 @@ static const struct pad_config early_gpio_table_id2[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -89,6 +91,8 @@ static const struct pad_config early_gpio_table_id2[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ @@ -108,6 +112,8 @@ static const struct pad_config early_gpio_table_id2[] = { }; static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), };