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mb/intel/jasperlake_rvp: Enable I2C4 for UFC 

This change updates devicetree to enable I2C4 bus required for the UFC

Change-Id: Iade1b64fa3dc890a896fb987fdc8d68db7db5e5f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
Sugnan Prabhu S 2020-08-21 18:05:17 +05:30 committed by Patrick Georgi
parent 4ddbc8b6ed
commit 65993e8233
1 changed files with 4 additions and 1 deletions
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5
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
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@ -94,7 +94,7 @@ chip soc/intel/jasperlake
[PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
}" }"
@ -149,6 +149,9 @@ chip soc/intel/jasperlake
.sda_hold = 36, .sda_hold = 36,
} }
}, },
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = { .i2c[5] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
}, },