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ryu: display: Add function to pass mode info to payload 

This change is intended for code sharing.

BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and rush

Change-Id: Ib83106f1c2d83c1d98b38567626f3169f2aec626
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f7414132aaaa6a98663852219e17acbe919d704
Original-Change-Id: Idedb0c16e33a630c954c04767592c3a75c49944b
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238944
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jimmy Zhang 2015-01-06 14:35:05 -08:00 committed by Patrick Georgi
parent 51b314b583
commit 65a4148695
3 changed files with 30 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/soc/nvidia/tegra132/dc.c
View File

@ -20,6 +20,7 @@
#include <arch/io.h>
#include <stdint.h>
#include <stdlib.h>
#include <edid.h>
#include <device/device.h>
#include <soc/nvidia/tegra/dc.h>
#include "chip.h"
@ -221,3 +222,28 @@ int tegra_dc_init(struct display_controller *disp_ctrl)
return 0;
}
/*
* Save mode to cb tables
*/
void pass_mode_info_to_payload(
struct soc_nvidia_tegra132_config *config)
{
struct edid edid;
/* Align bytes_per_line to 64 bytes as required by dc */
edid.bytes_per_line = ALIGN_UP((config->display_xres *
config->framebuffer_bits_per_pixel / 8), 64);
edid.x_resolution = edid.bytes_per_line /
(config->framebuffer_bits_per_pixel / 8);
edid.y_resolution = config->display_yres;
edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
" x_res x y_res: %d x %d, size: %d\n",
__func__, edid.bytes_per_line,
edid.framebuffer_bits_per_pixel,
edid.x_resolution, edid.y_resolution,
(edid.bytes_per_line * edid.y_resolution));
set_vbe_mode_info_valid(&edid, 0);
}

22
src/soc/nvidia/tegra132/dsi.c
View File

@ -952,26 +952,8 @@ void dsi_display_startup(device_t dev)
update_window(config);
printk(BIOS_INFO, "%s: display init done.\n", __func__);
/*
* Pass panel information to cb tables
*/
struct edid edid;
/* Align bytes_per_line to 64 bytes as required by dc */
edid.bytes_per_line = ALIGN_UP((config->display_xres *
config->framebuffer_bits_per_pixel / 8), 64);
edid.x_resolution = edid.bytes_per_line /
(config->framebuffer_bits_per_pixel / 8);
edid.y_resolution = config->display_yres;
edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
" x_res x y_res: %d x %d, size: %d\n",
__func__, edid.bytes_per_line,
edid.framebuffer_bits_per_pixel,
edid.x_resolution, edid.y_resolution,
(edid.bytes_per_line * edid.y_resolution));
set_vbe_mode_info_valid(&edid, 0);
/* Save panel information to cb tables */
pass_mode_info_to_payload(config);
/*
* After this point, it is payload's responsibility to allocate

2
src/soc/nvidia/tegra132/include/soc/display.h
View File

@ -47,4 +47,6 @@ int update_display_mode(struct display_controller *disp_ctrl,
void update_window(const struct soc_nvidia_tegra132_config *config);
void update_display_shift_clock_divider(struct display_controller *disp_ctrl,
u32 shift_clock_div);
void pass_mode_info_to_payload(
struct soc_nvidia_tegra132_config *config);
#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */