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soc/qualcomm/sc7280: DDR One-Time-Training Support 

Introduce DDR One-Time-Training Support
Device reboots without training from second iteration
and also DDR training data is 32kb size, hence update
required in memlayout and to sync with upstream changes
the Fmap size even got bumped up.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Ravi Kumar Bokka 2021-07-16 16:52:34 +05:30 committed by Shelley Chen
parent 1de2dd25f7
commit 65af8bbe72
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/google/herobrine/chromeos.fmd
View File

@ -17,7 +17,7 @@ FLASH@0x0 8M {
RW_VPD(PRESERVE) 32K
RW_NVRAM(PRESERVE) 16K
RW_DDR_TRAINING(PRESERVE) 8K
RW_MRC_CACHE(PRESERVE) 32K
RW_LIMITS_CFG(PRESERVE) 4K
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {

4
src/soc/qualcomm/sc7280/memlayout.ld
View File

@ -37,14 +37,14 @@ SECTIONS
STACK(0x1484B000, 16K)
VBOOT2_WORK(0x1484F000, 12K)
DMA_COHERENT(0x14853000, 8K)
REGION(ddr_training, 0x14855000, 8K, 4K)
REGION(qclib_serial_log, 0x14857000, 4K, 4K)
CBFS_MCACHE(0x14858000,16K)
REGION(ddr_information, 0x1485C000, 1K, 1K)
FMAP_CACHE(0x1485C400, 2K)
REGION(dcb, 0x1485E000, 32K, 4K)
REGION(pmic, 0x14866000, 96K, 4K)
REGION(qclib, 0x1487E000, 840K, 4K)
REGION(ddr_training, 0x1487E000, 32K, 4K)
REGION(qclib, 0x14886000, 800K, 4K)
BSRAM_END(0x14950000)
DRAM_START(0x80000000)