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soc/amd/cezanne: Add GRXS and GTXS method

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Add GRXS and GTXS support. Move the gpio method into common place.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Eric Lai 2021-04-09 11:50:48 +08:00 committed by Patrick Georgi
parent 6ada39e790
commit 65b0afe9a6
6 changed files with 58 additions and 47 deletions
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1
src/soc/amd/cezanne/Kconfig
View file

@ -37,6 +37,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS

3
src/soc/amd/common/block/acpi/Kconfig
View file

@ -4,3 +4,6 @@ config SOC_AMD_COMMON_BLOCK_ACPI
select ACPI_AMD_HARDWARE_SLEEP_VALUES
help
Select this option to use the AcpiMmio ACPI registers.
config SOC_AMD_COMMON_BLOCK_ACPI_GPIO
bool

1
src/soc/amd/common/block/acpi/Makefile.inc
View file

@ -9,5 +9,6 @@ smm-y += acpi.c
ramstage-y += pm_state.c
ramstage-y += tables.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO) += gpio.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI

52
src/soc/amd/common/block/acpi/gpio.c Normal file
View file

@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
#include <console/console.h>
#include <soc/gpio.h>
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num);
}

1
src/soc/amd/picasso/Kconfig
View file

@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS

47
src/soc/amd/picasso/acpi.c
View file

@ -364,50 +364,3 @@ void generate_cpu_entries(const struct device *device)
acpigen_write_name_integer("PCNT", logical_cores);
acpigen_pop_len();
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num);
}