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src: Get rid of non-local header treated as local 

Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-07-03 14:59:50 +02:00 committed by Patrick Georgi
parent 870f69e221
commit 65bb5434f6
11 changed files with 26 additions and 26 deletions
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2
src/cpu/amd/car/post_cache_as_ram.c
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@ -31,7 +31,7 @@
#include "cpu/amd/car/disable_cache_as_ram.c"
// For set_sysinfo_in_ram()
#include "northbridge/amd/amdfam10/raminit.h"
#include <northbridge/amd/amdfam10/raminit.h>
#if CONFIG_RAMTOP <= 0x100000
#error "You need to set CONFIG_RAMTOP greater than 1M"

2
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
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@ -24,7 +24,7 @@
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>

10
src/cpu/intel/haswell/romstage.c
View File

@ -37,12 +37,12 @@
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
#include "haswell.h"
#include "northbridge/intel/haswell/haswell.h"
#include "northbridge/intel/haswell/raminit.h"
#include "southbridge/intel/lynxpoint/pch.h"
#include "southbridge/intel/lynxpoint/me.h"
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <cpu/intel/romstage.h>
#include "haswell.h"
static inline void reset_system(void)
{

2
src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl
View File

@ -230,5 +230,5 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMDF10", "AMDACPI ", 100925440)
Z00A, 8
}
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
}

8
src/mainboard/asus/kcma-d8/dsdt.asl
View File

@ -39,8 +39,8 @@ DefinitionBlock (
0x00000001 /* OEM Revision */
)
{
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
#include "southbridge/amd/sr5650/acpi/sr5650.asl"
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
#include <southbridge/amd/sr5650/acpi/sr5650.asl>
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
@ -427,7 +427,7 @@ DefinitionBlock (
{
Name (_ADR, 0x00110000) // _ADR: Address
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
#include "southbridge/amd/sb700/acpi/sata.asl"
#include <southbridge/amd/sb700/acpi/sata.asl>
}
/* 0:12.0 SP5100 USB 0 */
@ -477,7 +477,7 @@ DefinitionBlock (
{
Name (_ADR, 0x00140001) // _ADR: Address
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
#include "southbridge/amd/sb700/acpi/ide.asl"
#include <southbridge/amd/sb700/acpi/ide.asl>
}
/* 0:14.3 SP5100 LPC */

4
src/mainboard/asus/kfsn4-dre/dsdt.asl
View File

@ -39,7 +39,7 @@ DefinitionBlock (
0x00000001 /* OEM Revision */
)
{
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
@ -404,7 +404,7 @@ DefinitionBlock (
Return (Local3)
}
#include "southbridge/nvidia/ck804/acpi/ck804.asl"
#include <southbridge/nvidia/ck804/acpi/ck804.asl>
/* PCI Routing Table Access */
Method (_PRT, 0, NotSerialized) {

8
src/mainboard/asus/kgpe-d16/dsdt.asl
View File

@ -39,8 +39,8 @@ DefinitionBlock (
0x00000001 /* OEM Revision */
)
{
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
#include "southbridge/amd/sr5650/acpi/sr5650.asl"
#include <northbridge/amd/amdfam10/amdfam10_util.asl>
#include <southbridge/amd/sr5650/acpi/sr5650.asl>
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
@ -427,7 +427,7 @@ DefinitionBlock (
{
Name (_ADR, 0x00110000) // _ADR: Address
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
#include "southbridge/amd/sb700/acpi/sata.asl"
#include <southbridge/amd/sb700/acpi/sata.asl>
}
/* 0:12.0 SP5100 USB 0 */
@ -477,7 +477,7 @@ DefinitionBlock (
{
Name (_ADR, 0x00140001) // _ADR: Address
Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
#include "southbridge/amd/sb700/acpi/ide.asl"
#include <southbridge/amd/sb700/acpi/ide.asl>
}
/* 0:14.3 SP5100 LPC */

6
src/mainboard/asus/p2b-ls/dsdt.asl
View File

@ -116,7 +116,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
Return (0x0B)
}
}
#include "southbridge/intel/i82371eb/acpi/intx.asl"
#include <southbridge/intel/i82371eb/acpi/intx.asl>
PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)
PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)
@ -174,7 +174,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
})
#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"
#include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl>
/* Begin southbridge block */
Device (PX40)
@ -230,7 +230,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
Return (BUF1)
}
}
#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"
#include <southbridge/intel/i82371eb/acpi/i82371eb.asl>
}
Device (PX43)
{

6
src/mainboard/asus/p2b/dsdt.asl
View File

@ -112,7 +112,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
Return (0x0B)
}
}
#include "southbridge/intel/i82371eb/acpi/intx.asl"
#include <southbridge/intel/i82371eb/acpi/intx.asl>
PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)
PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)
@ -160,7 +160,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
})
#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"
#include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl>
/* Begin southbridge block */
Device (PX40)
@ -216,7 +216,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
Return (BUF1)
}
}
#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"
#include <southbridge/intel/i82371eb/acpi/i82371eb.asl>
}
Device (PX43)
{

2
src/southbridge/intel/fsp_rangeley/romstage.c
View File

@ -27,7 +27,7 @@
#include <console/console.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <program_loading.h>
#include "northbridge/intel/fsp_rangeley/northbridge.h"
#include <northbridge/intel/fsp_rangeley/northbridge.h>
#include "southbridge/intel/fsp_rangeley/soc.h"
#include "southbridge/intel/fsp_rangeley/gpio.h"
#include "southbridge/intel/fsp_rangeley/romstage.h"

2
src/southbridge/intel/lynxpoint/early_pch.c
View File

@ -27,7 +27,7 @@
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#else
#include "southbridge/intel/common/gpio.h"
#include <southbridge/intel/common/gpio.h>
#endif
const struct rcba_config_instruction pch_early_config[] = {