This code gets us to a working linux boot on the alix1c. I have not tested
Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up comments, and just in general customizing for the 1c. The lxraminit change fixes a bug (&& used instead of ||), adds some debug prints which were VERY useful debugging the alix1c, changes fatal error messages from print_debug to print_emerg, and adds two functions: banner, which just prints out a string with a banner, and hcf, which print an emergency message and then pushes null bytes into the uart forever, just to make sure that no bytes get lost for any reason. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
3d02e1e0d8
commit
65bc460e01
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@ -205,7 +205,13 @@ void SetDelayControl(void)
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}
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}
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}
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print_debug("Try to write GLCP_DELAY_CONTROLS: hi ");
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print_debug_hex32(msr.hi);
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print_debug(" and lo ");
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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wrmsr(GLCP_DELAY_CONTROLS, msr);
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print_debug("SetDelayControl done\r\n");
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return;
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}
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@ -219,6 +225,7 @@ void cpuRegInit(void)
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/* Castle 2.0 BTM periodic sync period. */
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/* [40:37] 1 sync record per 256 bytes */
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print_debug("Castle 2.0 BTM periodic sync period.\r\n");
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msrnum = CPU_PF_CONF;
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msr = rdmsr(msrnum);
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msr.hi |= (0x8 << 5);
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@ -228,6 +235,7 @@ void cpuRegInit(void)
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* LX performance setting.
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* Enable Quack for fewer re-RAS on the MC
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*/
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print_debug("Enable Quack for fewer re-RAS on the MC\r\n");
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msrnum = GLIU0_ARB;
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msr = rdmsr(msrnum);
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msr.hi &= ~ARB_UPPER_DACK_EN_SET;
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@ -240,22 +248,28 @@ void cpuRegInit(void)
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msr.hi |= ARB_UPPER_QUACK_EN_SET;
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wrmsr(msrnum, msr);
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/* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
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/* GLIU port active enable, limit south pole masters
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* (AES and PCI) to one outstanding transaction.
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*/
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print_debug(" GLIU port active enable\r\n");
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msrnum = GLIU1_PORT_ACTIVE;
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msr = rdmsr(msrnum);
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msr.lo &= ~0x880;
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wrmsr(msrnum, msr);
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/* Set the Delay Control in GLCP */
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print_debug("Set the Delay Control in GLCP\r\n");
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SetDelayControl();
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/* Enable RSDC */
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print_debug("Enable RSDC\r\n");
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msrnum = CPU_AC_SMM_CTL;
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msr = rdmsr(msrnum);
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msr.lo |= SMM_INST_EN_SET;
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wrmsr(msrnum, msr);
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/* FPU imprecise exceptions bit */
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print_debug("FPU imprecise exceptions bit\r\n");
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msrnum = CPU_FPU_MSR_MODE;
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msr = rdmsr(msrnum);
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msr.lo |= FPU_IE_SET;
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@ -263,12 +277,14 @@ void cpuRegInit(void)
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/* Power Savers (Do after BIST) */
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/* Enable Suspend on HLT & PAUSE instructions */
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print_debug("Enable Suspend on HLT & PAUSE instructions\r\n");
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msrnum = CPU_XC_CONFIG;
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msr = rdmsr(msrnum);
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msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
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wrmsr(msrnum, msr);
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/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
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print_debug("Enable SUSP and allow TSC to run in Suspend\r\n");
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msrnum = CPU_BC_CONF_0;
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msr = rdmsr(msrnum);
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msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
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@ -286,6 +302,7 @@ void cpuRegInit(void)
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#endif
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/* Setup throttling delays to proper mode if it is ever enabled. */
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print_debug("Setup throttling delays to proper mode\r\n");
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msrnum = GLCP_TH_OD;
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msr.hi = 0;
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msr.lo = 0x00000603C;
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@ -20,6 +20,7 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <spd.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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@ -37,13 +38,70 @@
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#define POST_CODE(x) outb(x, 0x80)
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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/* The alix1c has no SMBUS; the setup is hard-wired. */
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void cs5536_enable_smbus(void)
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{
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}
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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/* the part is a hynix hy5du121622ctp-d43
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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* Hynix
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* DDR SDRAM (5D)
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* VDD 2.5 VDDQ 2.5 (U)
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* 512M 8K REFRESH (12)
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* x16 (16)
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* 4banks (2)
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* SSTL_2 (2)
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* 4th GEN die (C)
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* Normal Power Consumption (<blank> )
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* TSOP (T)
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* Single Die (<blank>)
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* Lead Free (P)
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* DDR400 3-3-3 (D43)
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*/
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/* spd array */
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static u8 spdbytes[] = {
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[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
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[SPD_BANK_DENSITY] = 0x40,
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[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
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[SPD_MEMORY_TYPE] = 7,
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[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* This is a guess for tRAC value */
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[SPD_MODULE_ATTRIBUTES] = 0xff, /* fix me later when we figure out */
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[SPD_NUM_BANKS_PER_SDRAM] = 4,
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[SPD_PRIMARY_SDRAM_WIDTH] = 8,
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/* alix1c is 1 bank. */
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[SPD_NUM_DIMM_BANKS] = 1,
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[SPD_NUM_COLUMNS] = 0xa,
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[SPD_NUM_ROWS] = 3,
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[SPD_REFRESH] = 0x3a,
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[SPD_SDRAM_CYCLE_TIME_2ND] = 60,
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[SPD_SDRAM_CYCLE_TIME_3RD] = 75,
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[SPD_tRAS] = 40,
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[SPD_tRCD] = 15,
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[SPD_tRFC] = 70,
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[SPD_tRP] = 15,
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[SPD_tRRD] = 10,
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};
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static u8 spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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print_debug("spd_read_byte dev ");
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print_debug_hex8(device);
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if (device != (0x50<<1)){
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print_debug(" returns 0xff\n");
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return 0xff;
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}
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print_debug(" addr ");
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print_debug_hex8(address);
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print_debug(" returns ");
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print_debug_hex8(spdbytes[address]);
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print_debug("\r\n");
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return spdbytes[address];
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}
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#define ManualConf 0 /* Do automatic strapped PLL config */
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@ -83,13 +141,12 @@ static void mb_gpio_init(void)
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void cache_as_ram_main(void)
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{
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static const struct mem_controller memctrl[] = {
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{.channel0 = {0x50}},
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};
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extern void RestartCAR();
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POST_CODE(0x01);
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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SystemPreInit();
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msr_init();
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@ -114,24 +171,34 @@ void cache_as_ram_main(void)
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/* Check memory */
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ram_check(0x00000000, 640 * 1024);
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/* Switch from Cache as RAM to real RAM */
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/* There are two ways we could think about this.
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1. If we are using the auto.inc ROMCC way, the stack is going to be re-setup in the code following this code.
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Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
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2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
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That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
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as the rest of LinuxBIOS. If that is the case we can just do a wbinvd. The stack will be written into real
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RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
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where LB would like it, you need to write some code to do a copy from cache to RAM
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We use method 1 on Norwich and on this board too.
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*/
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/* Switch from Cache as RAM to real RAM
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* There are two ways we could think about this.
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*
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* 1. If we are using the auto.inc ROMCC way, the stack is
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* going to be re-setup in the code following this code. Just
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* wbinvd the stack to clear the cache tags. We don't care
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* where the stack used to be.
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*
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* 2. This file is built as a normal .c -> .o and linked in
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* etc. The stack might be used to return etc. That means we
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* care about what is in the stack. If we are smart we set
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* the CAR stack to the same location as the rest of
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* LinuxBIOS. If that is the case we can just do a wbinvd.
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* The stack will be written into real RAM that is now setup
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* and we continue like nothing happened. If the stack is
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* located somewhere other than where LB would like it, you
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* need to write some code to do a copy from cache to RAM
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*
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* We use method 1 on Norwich and on this board too.
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*/
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POST_CODE(0x02);
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print_err("POST 02\n");
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__asm__("wbinvd\n");
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print_err("Past wbinvd\n");
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/* we are finding the return does not work on this board. Explicitly call the label that is
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* after the call to us. This is gross, but sometimes at this level it is the only way out
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/* we are finding the return does not work on this
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* board. Explicitly call the label that is after the call to
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* us. This is gross, but sometimes at this level it is the
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* only way out
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*/
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done_cache_as_ram_main();
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}
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@ -27,6 +27,23 @@ static const unsigned char NumColAddr[] = {
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0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
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};
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void banner(char *s)
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{
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print_emerg("===========================");
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print_emerg(s);
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print_emerg("======================================\r\n");
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}
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void hcf(void)
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{
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print_emerg("DIE\r\n");
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/* this guarantees we flush the UART fifos (if any) and also
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* ensures that things, in general, keep going so no debug output
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* is lost
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*/
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while (1)
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print_emerg_char(0);
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}
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static void auto_size_dimm(unsigned int dimm)
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{
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uint32_t dimm_setting;
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@ -36,33 +53,37 @@ static void auto_size_dimm(unsigned int dimm)
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dimm_setting = 0;
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banner("Check present");
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/* Check that we have a dimm */
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if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
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return;
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}
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banner("MODBANKS");
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/* Field: Module Banks per DIMM */
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/* EEPROM byte usage: (5) Number of DIMM Banks */
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spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
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if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
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print_debug("Number of module banks not compatible\n");
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if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
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print_emerg("Number of module banks not compatible\n");
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POST_CODE(ERROR_BANK_SET);
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__asm__ __volatile__("hlt\n");
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hcf();
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}
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dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
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banner("FIELDBANKS");
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/* Field: Banks per SDRAM device */
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/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
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spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
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if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
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print_debug("Number of device banks not compatible\n");
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if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
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print_emerg("Number of device banks not compatible\n");
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POST_CODE(ERROR_BANK_SET);
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__asm__ __volatile__("hlt\n");
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hcf();
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}
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dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
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banner("SPDNUMROWS");
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/*; Field: DIMM size
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*; EEPROM byte usage: (3) Number or Row Addresses
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*; EEPROM byte usage: (3) Number of Row Addresses
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*; (4) Number of Column Addresses
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*; (5) Number of DIMM Banks
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*; (31) Module Bank Density
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@ -70,24 +91,29 @@ static void auto_size_dimm(unsigned int dimm)
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*/
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if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
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|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
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print_debug("Assymetirc DIMM not compatible\n");
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print_emerg("Assymetirc DIMM not compatible\n");
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POST_CODE(ERROR_UNSUPPORTED_DIMM);
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__asm__ __volatile__("hlt\n");
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hcf();
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}
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banner("SPDBANKDENSITY");
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dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
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banner("DIMMSIZE");
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dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
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dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
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/* Module Density * Module Banks */
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dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
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banner("BEFORT CTZ");
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dimm_size = __builtin_ctz(dimm_size);
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banner("TEST DIMM SIZE>8");
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if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
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print_debug("Only support up to 1 GB per DIMM\n");
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print_emerg("Only support up to 1 GB per DIMM\n");
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POST_CODE(ERROR_DENSITY_DIMM);
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__asm__ __volatile__("hlt\n");
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hcf();
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}
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dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
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banner("PAGESIZE");
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/*; Field: PAGE size
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*; EEPROM byte usage: (4) Number of Column Addresses
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@ -113,18 +139,22 @@ static void auto_size_dimm(unsigned int dimm)
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*;it adds 3 to get 10, then does 2^10=1K. Get it?*/
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spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
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banner("MAXCOLADDR");
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if (spd_byte > MAX_COL_ADDR) {
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print_debug("DIMM page size not compatible\n");
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print_emerg("DIMM page size not compatible\n");
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POST_CODE(ERROR_SET_PAGE);
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__asm__ __volatile__("hlt\n");
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hcf();
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}
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banner(">12address test");
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spd_byte -= 7;
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if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */
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spd_byte = 7; /* which means >32k so set to disabled */
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}
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dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
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banner("RDMSR CF07");
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msr = rdmsr(MC_CF07_DATA);
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banner("WRMSR CF07");
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if (dimm == DIMM0) {
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msr.hi &= 0xFFFF0000;
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msr.hi |= dimm_setting;
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@ -133,6 +163,7 @@ static void auto_size_dimm(unsigned int dimm)
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msr.hi |= dimm_setting << 16;
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}
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wrmsr(MC_CF07_DATA, msr);
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banner("ALL DONE");
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}
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static void checkDDRMax(void)
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@ -152,9 +183,9 @@ static void checkDDRMax(void)
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/* I don't think you need this check.
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if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
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print_debug("DIMM overclocked. Check GeodeLink Speed\n");
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print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
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POST_CODE(POST_PLL_MEM_FAIL);
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__asm__ __volatile__("hlt\n");
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hcf();
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} */
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/* Use the slowest DIMM */
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@ -167,9 +198,9 @@ static void checkDDRMax(void)
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/* current speed > max speed? */
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if (GeodeLinkSpeed() > speed) {
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print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
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print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n");
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POST_CODE(POST_PLL_MEM_FAIL);
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__asm__ __volatile__("hlt\n");
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hcf();
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}
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}
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|
@ -308,9 +339,9 @@ static void setCAS(void)
|
|||
} else if ((casmap0 &= casmap1)) {
|
||||
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
|
||||
} else {
|
||||
print_debug("DIMM CAS Latencies not compatible\r\n");
|
||||
print_emerg("DIMM CAS Latencies not compatible\r\n");
|
||||
POST_CODE(ERROR_DIFF_DIMMS);
|
||||
__asm__ __volatile__("hlt\n");
|
||||
hcf();
|
||||
}
|
||||
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
|
|
@ -500,7 +531,7 @@ static void EnableMTest(void)
|
|||
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
|
||||
wrmsr(MC_CFCLK_DBUG, msr);
|
||||
|
||||
print_debug("Enabled MTest for TLA debug\r\n");
|
||||
print_info("Enabled MTest for TLA debug\r\n");
|
||||
}
|
||||
|
||||
static void sdram_set_registers(const struct mem_controller *ctrl)
|
||||
|
|
@ -537,43 +568,53 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
|||
{
|
||||
uint8_t spd_byte;
|
||||
|
||||
banner("sdram_set_spd_register\n");
|
||||
POST_CODE(POST_MEM_SETUP); // post_70h
|
||||
|
||||
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
|
||||
banner("Check DIMM 0");
|
||||
/* Check DIMM is not Register and not Buffered DIMMs. */
|
||||
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
|
||||
print_debug("DIMM0 NOT COMPATIBLE\r\n");
|
||||
print_emerg("DIMM0 NOT COMPATIBLE\r\n");
|
||||
POST_CODE(ERROR_UNSUPPORTED_DIMM);
|
||||
__asm__ __volatile__("hlt\n");
|
||||
hcf();
|
||||
}
|
||||
banner("Check DIMM 1");
|
||||
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
|
||||
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
|
||||
print_debug("DIMM1 NOT COMPATIBLE\n");
|
||||
print_emerg("DIMM1 NOT COMPATIBLE\n");
|
||||
POST_CODE(ERROR_UNSUPPORTED_DIMM);
|
||||
__asm__ __volatile__("hlt\n");
|
||||
hcf();
|
||||
}
|
||||
|
||||
POST_CODE(POST_MEM_SETUP2); // post_72h
|
||||
banner("Check DDR MAX");
|
||||
|
||||
/* Check that the memory is not overclocked. */
|
||||
checkDDRMax();
|
||||
|
||||
/* Size the DIMMS */
|
||||
POST_CODE(POST_MEM_SETUP3); // post_73h
|
||||
banner("AUTOSIZE DIMM 0");
|
||||
auto_size_dimm(DIMM0);
|
||||
POST_CODE(POST_MEM_SETUP4); // post_74h
|
||||
banner("AUTOSIZE DIMM 1");
|
||||
auto_size_dimm(DIMM1);
|
||||
|
||||
/* Set CAS latency */
|
||||
banner("set cas latency");
|
||||
POST_CODE(POST_MEM_SETUP5); // post_75h
|
||||
setCAS();
|
||||
|
||||
/* Set all the other latencies here (tRAS, tRP....) */
|
||||
banner("set all latency");
|
||||
set_latencies();
|
||||
|
||||
/* Set Extended Mode Registers */
|
||||
banner("set emrs");
|
||||
set_extended_mode_registers();
|
||||
|
||||
banner("set ref rate");
|
||||
/* Set Memory Refresh Rate */
|
||||
set_refresh_rate();
|
||||
|
||||
|
|
@ -607,9 +648,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
msr = rdmsr(MC_CF07_DATA);
|
||||
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
|
||||
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
|
||||
print_debug("No memory in the system\r\n");
|
||||
print_emerg("No memory in the system\r\n");
|
||||
POST_CODE(ERROR_NO_DIMMS);
|
||||
__asm__ __volatile__("hlt\n");
|
||||
hcf();
|
||||
}
|
||||
|
||||
/* Set CKEs */
|
||||
|
|
@ -717,7 +758,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
msr.lo |= (209 << 8); /* bits[15:8] = 209 */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
print_debug("DRAM controller init done.\n");
|
||||
print_emerg("DRAM controller init done.\n");
|
||||
POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
|
||||
|
||||
/* make sure there is nothing stale in the cache */
|
||||
|
|
@ -749,6 +790,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
msr.lo |= 1;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
print_debug("RAM DLL lock\n");
|
||||
print_info("RAM DLL lock\n");
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue