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Ignore RAMTOP for MTRRs 

Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.

With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.

Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-19 20:38:41 +03:00
parent c5400efc11
commit 65cc526f6f
18 changed files with 35 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/x86/include/arch/memlayout.h
View File

@ -24,4 +24,8 @@
#define ARCH_STAGE_HAS_BSS_SECTION 0
#endif
#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
# error "CONFIG_RAMTOP not configured"
#endif
#endif /* __ARCH_MEMLAYOUT_H */

4
src/cpu/amd/agesa/s3_resume.c
View File

@ -75,11 +75,11 @@ static void set_resume_cache(void)
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
wrmsr(SYSCFG_MSR, msr);
/* Enable caching for 0 - coreboot ram using variable mtrr */
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
msr.lo = 0 | MTRR_TYPE_WRBACK;
msr.hi = 0;
wrmsr(MTRR_PHYS_BASE(0), msr);
msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(0), msr);

4
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -175,8 +175,8 @@ void cache_as_ram_new_stack (void)
disable_cache_as_ram_bsp();
disable_cache();
/* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
if (acpi_is_wakeup_s3()) {

2
src/cpu/amd/family_10h-family_15h/init_cpus.c
View File

@ -519,7 +519,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
/* AP is ready, configure MTRRs and go to sleep */
if (set_mtrrs)
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
printk(BIOS_DEBUG, "Disabling CAR on AP %02x\n", apicid);
if (is_fam15h()) {

2
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -326,7 +326,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
apicid);
}
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
#if CONFIG_K8_REV_F_SUPPORT
#if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo,

4
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -173,12 +173,12 @@ static void set_init_ecc_mtrrs(void)
wrmsr(MTRR_PHYS_MASK(i), zero);
}
/* Write back cache the first 1MB */
/* Write back cache from 0x0 to CACHE_TMP_RAMTOP. */
msr.hi = 0x00000000;
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
wrmsr(MTRR_PHYS_BASE(0), msr);
msr.hi = 0x000000ff;
msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
msr.lo = ~((CACHE_TMP_RAMTOP) - 1) | 0x800;
wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default type to write combining */

4
src/cpu/amd/pi/s3_resume.c
View File

@ -271,11 +271,11 @@ static void set_resume_cache(void)
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
wrmsr(SYSCFG_MSR, msr);
/* Enable caching for 0 - coreboot ram using variable mtrr */
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
msr.lo = 0 | MTRR_TYPE_WRBACK;
msr.hi = 0;
wrmsr(MTRR_PHYS_BASE(0), msr);
msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(0), msr);

2
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@ -388,7 +388,7 @@ no_msr_11e:
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
rdmsr
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#if CACHE_ROM_SIZE

4
src/cpu/intel/haswell/romstage.c
View File

@ -119,9 +119,9 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;

2
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@ -233,7 +233,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr

2
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@ -243,7 +243,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr

2
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -182,7 +182,7 @@ clear_mtrrs:
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr

4
src/cpu/via/car/cache_as_ram.inc
View File

@ -225,7 +225,7 @@ testok:
movl $(MTRR_DEF_TYPE_EN), %eax
wrmsr
/* Enable caching for 0..CONFIG_RAMTOP. */
/* Enable caching for 0..CACHE_TMP_RAMTOP. */
movl $MTRR_PHYS_BASE(0), %ecx
xorl %edx, %edx
movl $(0x0 | MTRR_TYPE_WRBACK), %eax
@ -233,7 +233,7 @@ testok:
movl $MTRR_PHYS_MASK(0), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/* Cache XIP_ROM area to speedup coreboot code. */

4
src/drivers/intel/fsp1_1/stack.c
View File

@ -88,9 +88,9 @@ void *setup_stack_and_mtrrs(void)
* +0: Number of variable MTRRs to clear
*/
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push32(slot, 0); /* upper base */
slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;

12
src/include/cpu/x86/mtrr.h
View File

@ -91,9 +91,11 @@ int get_free_var_mtrr(void);
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
# error "CONFIG_RAMTOP not configured"
#endif
/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set
* as write-back cacheable to speed up ramstage decompression.
* Note MTRR boundaries, must be power of two.
*/
#define CACHE_TMP_RAMTOP (16<<20)
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
@ -122,8 +124,4 @@ int get_free_var_mtrr(void);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#endif
#endif /* CPU_X86_MTRR_H */

4
src/northbridge/intel/i3100/raminit.c
View File

@ -928,9 +928,9 @@ static void set_receive_enable(const struct mem_controller *ctrl)
static void cache_ramstage(void)
{
/* Enable caching for lower 1MB and ram stage using variable mtrr */
/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
disable_cache();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
}

4
src/soc/intel/baytrail/romstage/romstage.c
View File

@ -312,9 +312,9 @@ static void *setup_stack_and_mttrs(void)
slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;

4
src/soc/intel/broadwell/romstage/stack.c
View File

@ -83,9 +83,9 @@ void *setup_stack_and_mttrs(void)
slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;