Remove inline from FAM10 CPU initialization functions.
This doesn't save any space for me but it is the right thing to allow GCC to optimize. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -25,21 +25,21 @@
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// if we are tight of CAR stack, disable it
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#define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
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static inline void print_debug_fv(const char *str, u32 val)
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static void print_debug_fv(const char *str, u32 val)
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{
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#if FAM10_SET_FIDVID_DEBUG == 1
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printk_debug("%s%x\n", str, val);
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#endif
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}
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static inline void print_debug_fv_8(const char *str, u8 val)
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static void print_debug_fv_8(const char *str, u8 val)
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{
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#if FAM10_SET_FIDVID_DEBUG == 1
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printk_debug("%s%02x\n", str, val);
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#endif
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}
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static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
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static void print_debug_fv_64(const char *str, u32 val, u32 val2)
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{
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#if FAM10_SET_FIDVID_DEBUG == 1
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printk_debug("%s%x%x\n", str, val, val2);
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@ -30,24 +30,24 @@
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#define FAM10_SET_FIDVID_CORE0_ONLY 0
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#endif
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static inline void print_initcpu8 (const char *strval, u8 val)
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static void print_initcpu8 (const char *strval, u8 val)
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{
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printk_debug("%s%02x\n", strval, val);
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}
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static inline void print_initcpu8_nocr (const char *strval, u8 val)
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static void print_initcpu8_nocr (const char *strval, u8 val)
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{
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printk_debug("%s%02x", strval, val);
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}
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static inline void print_initcpu16 (const char *strval, u16 val)
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static void print_initcpu16 (const char *strval, u16 val)
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{
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printk_debug("%s%04x\n", strval, val);
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}
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static inline void print_initcpu(const char *strval, u32 val)
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static void print_initcpu(const char *strval, u32 val)
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{
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printk_debug("%s%08x\n", strval, val);
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}
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@ -59,7 +59,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid);
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void cpuSetAMDMSR(void);
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#if PCI_IO_CFG_EXT == 1
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static inline void set_EnableCf8ExtCfg(void)
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static void set_EnableCf8ExtCfg(void)
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{
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// set the NB_CFG[46]=1;
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msr_t msr;
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@ -69,7 +69,7 @@ static inline void set_EnableCf8ExtCfg(void)
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wrmsr(NB_CFG_MSR, msr);
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}
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#else
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static inline void set_EnableCf8ExtCfg(void) { }
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static void set_EnableCf8ExtCfg(void) { }
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#endif
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@ -78,7 +78,7 @@ static inline void set_EnableCf8ExtCfg(void) { }
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/* because we will use gs to store hi, so need to make sure lo can start
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from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
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static inline void set_pci_mmio_conf_reg(void)
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static void set_pci_mmio_conf_reg(void)
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{
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#if MMCONF_SUPPORT
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msr_t msr;
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@ -184,7 +184,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range,
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}
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/* FIXME: Duplicate of what is in lapic.h? */
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static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
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static int lapic_remote_read(int apicid, int reg, u32 *pvalue)
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{
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int timeout;
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u32 status;
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@ -24,7 +24,7 @@
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#include "cpu/amd/quadcore/quadcore_id.c"
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static inline u32 get_core_num_in_bsp(u32 nodeid)
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static u32 get_core_num_in_bsp(u32 nodeid)
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{
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u32 dword;
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dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
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@ -34,7 +34,7 @@ static inline u32 get_core_num_in_bsp(u32 nodeid)
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}
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#if SET_NB_CFG_54 == 1
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static inline u8 set_apicid_cpuid_lo(void)
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static u8 set_apicid_cpuid_lo(void)
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{
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// set the NB_CFG[54]=1; why the OS will be happy with that ???
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msr_t msr;
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@ -46,12 +46,12 @@ static inline u8 set_apicid_cpuid_lo(void)
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}
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#else
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static inline void set_apicid_cpuid_lo(void) { }
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static void set_apicid_cpuid_lo(void) { }
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#endif
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static inline void real_start_other_core(u32 nodeid, u32 cores)
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static void real_start_other_core(u32 nodeid, u32 cores)
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{
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u32 dword;
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@ -78,7 +78,7 @@ static inline void real_start_other_core(u32 nodeid, u32 cores)
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}
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//it is running on core0 of node0
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static inline void start_other_cores(void)
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static void start_other_cores(void)
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{
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u32 nodes;
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u32 nodeid;
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@ -32,7 +32,7 @@ u32 read_nb_cfg_54(void)
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return ( ( msr.hi >> (54-32)) & 1);
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}
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static inline u32 get_initial_apicid(void)
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static u32 get_initial_apicid(void)
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{
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return ((cpuid_ebx(1) >> 24) & 0xff);
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}
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@ -67,12 +67,12 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
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return id;
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}
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static inline u32 get_core_num(void)
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static u32 get_core_num(void)
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{
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return (cpuid_ecx(0x80000008) & 0xff);
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}
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static inline struct node_core_id get_node_core_id_x(void) {
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static struct node_core_id get_node_core_id_x(void) {
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return get_node_core_id( read_nb_cfg_54() );
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}
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@ -102,7 +102,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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static void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_HUB 0x18
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int ret,i;
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@ -119,7 +119,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
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}
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static inline int spd_read_byte(u32 device, u32 address)
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static int spd_read_byte(u32 device, u32 address)
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{
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int result;
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result = smbus_read_byte(device, address);
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@ -60,7 +60,7 @@ static inline void _cpu_id(u32 addr, u32 *val)
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}
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static inline u32 bsr(u32 x)
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static u32 bsr(u32 x)
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{
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u8 i;
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u32 ret = 0;
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@ -77,7 +77,7 @@ static inline u32 bsr(u32 x)
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}
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static inline u32 bsf(u32 x)
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static u32 bsf(u32 x)
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{
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u8 i;
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u32 ret = 32;
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@ -65,7 +65,7 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat,
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#define DQS_TRAIN_DEBUG 0
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static inline void print_debug_dqs(const char *str, u32 val, u8 level)
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static void print_debug_dqs(const char *str, u32 val, u8 level)
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{
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#if DQS_TRAIN_DEBUG > 0
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if (DQS_TRAIN_DEBUG >= level) {
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@ -74,7 +74,7 @@ static inline void print_debug_dqs(const char *str, u32 val, u8 level)
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#endif
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}
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static inline void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level)
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static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level)
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{
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#if DQS_TRAIN_DEBUG > 0
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if (DQS_TRAIN_DEBUG >= level) {
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