intel romstage: Use run_ramstage()

Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15461
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/haswell/romstage.c

@@ -26,10 +26,10 @@
 #include <timestamp.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
-#include <arch/stages.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <cbmem.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -283,7 +283,7 @@ void romstage_after_car(void)
 		acpi_prepare_for_resume();
 
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 }
 
 

src/drivers/intel/fsp1_1/romstage.c

@@ -17,7 +17,6 @@
 #include <stddef.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
-#include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <boardid.h>
 #include <console/console.h>
@@ -29,6 +28,7 @@
 #include <elog.h>
 #include <fsp/romstage.h>
 #include <reset.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <smbios.h>
 #include <soc/intel/common/mrc_cache.h>
@@ -187,7 +187,7 @@ void romstage_common(struct romstage_params *params)
 void after_cache_as_ram_stage(void)
 {
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 	die("ERROR - Failed to load ramstage!");
 }
 

src/mainboard/intel/cougar_canyon2/romstage.c

@@ -28,6 +28,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <halt.h>
+#include <program_loading.h>
 #include <reset.h>
 #include <superio/smsc/sio1007/chip.h>
 #include <fsp_util.h>
@@ -39,7 +40,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include "gpio.h"
-#include <arch/stages.h>
 
 #define SIO_PORT 0x164e
 
@@ -303,7 +303,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	post_code(0x4f);
 
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 	while (1);
 }
 

src/soc/intel/baytrail/romstage/romstage.c

@@ -16,7 +16,6 @@
 #include <stddef.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
-#include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
 #include <cbfs.h>
@@ -26,6 +25,7 @@
 #include <ec/google/chromeec/ec.h>
 #endif
 #include <elog.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
@@ -247,7 +247,7 @@ void romstage_common(struct romstage_params *params)
 void asmlinkage romstage_after_car(void)
 {
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 	while (1);
 }
 

src/soc/intel/broadwell/romstage/romstage.c

@@ -18,7 +18,6 @@
 #include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
-#include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
 #include <cbfs.h>
@@ -26,6 +25,7 @@
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
 #include <tpm.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
@@ -129,7 +129,7 @@ void romstage_common(struct romstage_params *params)
 void asmlinkage romstage_after_car(void)
 {
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 	while (1);
 }
 

src/soc/intel/fsp_baytrail/romstage/romstage.c

@@ -19,11 +19,11 @@
 #include <lib.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
-#include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
 #include <soc/gpio.h>
@@ -267,7 +267,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 	post_code(0x4f);
 
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 	while (1);
 }
 

src/soc/intel/fsp_broadwell_de/romstage/romstage.c

@@ -19,9 +19,9 @@
 #include <lib.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
-#include <arch/stages.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
 #include <version.h>
@@ -110,7 +110,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 
 	/* Load the ramstage. */
 	post_code(0x4e);
-	copy_and_run();
+	run_ramstage();
 	while (1);
 }
 

src/southbridge/intel/fsp_i89xx/romstage.c

@@ -21,7 +21,6 @@
 #include <timestamp.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
-#include <arch/stages.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
@@ -31,6 +30,7 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <halt.h>
+#include <program_loading.h>
 #include <reset.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <northbridge/intel/fsp_sandybridge/northbridge.h>
@@ -214,7 +214,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 
 	timestamp_add_now(TS_END_ROMSTAGE);
 
-	copy_and_run();
+	run_ramstage();
 }
 
 uint64_t get_initial_timestamp(void)

src/southbridge/intel/fsp_rangeley/romstage.c

@@ -26,12 +26,12 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
+#include <program_loading.h>
 #include "northbridge/intel/fsp_rangeley/northbridge.h"
 #include "southbridge/intel/fsp_rangeley/soc.h"
 #include "southbridge/intel/fsp_rangeley/gpio.h"
 #include "southbridge/intel/fsp_rangeley/romstage.h"
 #include <arch/cpu.h>
-#include <arch/stages.h>
 #include <cpu/x86/msr.h>
 #include "gpio.h"
 
@@ -129,7 +129,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	post_code(0x4f);
 
 	/* Load the ramstage. */
-	copy_and_run();
+	run_ramstage();
 	while (1);
 }